| File | Description |
|---|
| nco80.v | A MegaCore® function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software. |
| nco80_bb.v | Verilog HDL black-box file for the MegaCore function variation. Use this file when using a third-party EDA tool to synthesize your design. |
| nco80.bsf | Quartus® II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor. |
| nco80_st.v | Generated NCO synthesizable netlist. This file is required for Quartus II synthesis. It will be added to your Quartus II project |
| nco80.vo | Verilog HDL IP Functional Simulation model |
| nco80_tb.v | Verilog HDL Testbench |
| nco80_vo_msim.tcl | ModelSim TCL Script to run the Verilog HDL IP Functional Simulation model and generated Verilog HDL testbench in the ModelSim simulation software |
| nco80_wave.do | ModelSim Waveform File |
| nco80_model.m | MATLAB m-file describing a MATLAB bit-accurate model. |
| nco80_tb.m | MATLAB Testbench |
| nco80_sin_f.hex | Intel Hex-format ROM initialization file. |
| nco80_cos_f.hex | Intel Hex-format ROM initialization file. |
| nco80_sin_c.hex | Intel Hex-format ROM initialization file. |
| nco80_cos_c.hex | Intel Hex-format ROM initialization file. |
| nco80.vec | Quartus II Vector File. |
| nco80_nativelink.tcl | A Tcl script that can be used to assign NativeLink simulation testbench settings to the Quartus II project |
| nco80.qip | Contains Quartus II project information for your MegaCore function variation. |
| nco80.html | The MegaCore function report file. |