| File | Description |
|---|
| nco72.v | A MegaCore® function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software. |
| nco72_bb.v | Verilog HDL black-box file for the MegaCore function variation. Use this file when using a third-party EDA tool to synthesize your design. |
| nco72.bsf | Quartus® II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor. |
| nco72_st.v | Generated NCO synthesizable netlist. This file is required for Quartus II synthesis. It will be added to your Quartus II project |
| nco72.vo | Verilog HDL IP Functional Simulation model |
| nco72_tb.v | Verilog HDL Testbench |
| nco72_vo_msim.tcl | Modelsim TCL Script to run the Verilog HDL IP Functional Simulation model and generated Verilog HDL testbench in the Modelsim simulation software |
| nco72_wave.do | Modelsim Waveform File |
| nco72_model.m | Matlab m-file describing a Matlab bit-accurate model. |
| nco72_tb.m | Matlab Testbench |
| nco72_sin_f.hex | Intel Hex-format ROM initialization file. |
| nco72_cos_f.hex | Intel Hex-format ROM initialization file. |
| nco72_sin_c.hex | Intel Hex-format ROM initialization file. |
| nco72_cos_c.hex | Intel Hex-format ROM initialization file. |
| nco72.vec | Quartus Vector File. |
| nco72.qip | Contains Quartus II project information for your MegaCore function variation. |
| nco72.html | The MegaCore function report file. |