// --------------------------------------------------------------------
// Copyright (c) 2007 by Terasic Technologies Inc. 
// --------------------------------------------------------------------
//
// Permission:
//
//   Terasic grants permission to use and modify this code for use
//   in synthesis for all Terasic Development Boards and Altera Development 
//   Kits made by Terasic.  Other use of this code, including the selling 
//   ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL/Verilog or C/C++ source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Terasic provides no warranty regarding the use 
//   or functionality of this code.
//
// --------------------------------------------------------------------
//           
//                     Terasic Technologies Inc
//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
//                     HsinChu County, Taiwan
//                     302
//
//                     web: http://www.terasic.com/
//                     email: support@terasic.com
//
// --------------------------------------------------------------------

#ifndef ISP1761_REGISTER_H_
#define ISP1761_REGISTER_H_

//#include "isp1761_host_register.h"
//#include "isp1761_device_register.h"

//OTG Registers
#define  OTG_CONTROL                          0x374

#define     HC_INTENABLE_REG            0x314   /* Interrupt enable Register */
//RR#define     HC_OTG_TIMER1_REG               0x370   /* OTG Timer 1 Register (read only) */
//RR#define     HC_OTG_TIMER2_REG               0x374   /* OTG Timer 2 Register */
//RR#define     HC_OTG_STATUS1_REG              0x378   /* OTG Status 1 Register */
//RR#define     HC_OTG_STATUS2_REG              0x37C   /* OTG Status 2 Register */
//RR#define     HC_OTG_SC_REG                   0x380   /* OTG Status Change Register */
//RR#define     HC_OTG_SC_IE_REG                0x384   /* OTG Status Change Interrupt Enable Register */

#define  HW_MODE_REG                         0x300   /* H/W Mode Register  */


#endif /*ISP1761_REGISTER_H_*/