// --------------------------------------------------------------------
// Copyright (c) 2007 by Terasic Technologies Inc. 
// --------------------------------------------------------------------
//
// Permission:
//
//   Terasic grants permission to use and modify this code for use
//   in synthesis for all Terasic Development Boards and Altera Development 
//   Kits made by Terasic.  Other use of this code, including the selling 
//   ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL/Verilog or C/C++ source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Terasic provides no warranty regarding the use 
//   or functionality of this code.
//
// --------------------------------------------------------------------
//           
//                     Terasic Technologies Inc
//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
//                     HsinChu County, Taiwan
//                     302
//
//                     web: http://www.terasic.com/
//                     email: support@terasic.com
//
// --------------------------------------------------------------------
// Author: Richard Chang

// 0626_2008, richard, 
//  remove delay in HAL1761_RegWrite32 & HAL1761_RegRead32

#include <io.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <string.h>
#include "system.h"
#include "isp1761_hal_nios2.h"
#include "isp1761_register.h"
#include "terasic_includes.h"


#ifdef DEBUG_ISP1761_HAL
    #define DEBUG_OUT(x) {printf("[UHAL]"); printf x;}
    #define DEBUG_ERR(x) {printf("[UHAL_ERR]"); printf x;}
#else
    #define DEBUG_OUT(x) 
    #define DEBUG_ERR(x)
#endif   



#define IO_DELAY(x)    OS_udelay(x)
#define WRITE_DELAY       2  
#define READ_DELAY        1 



//======== Fundametal USB Register Access Function =======

void HAL1761_RegWrite32(alt_u32 Addr, alt_u32 data32){
#ifdef DATA_BUS_16BIT_WIDTH  
    IOWR_16DIRECT(ISP1761_BASE, Addr, data32 & 0xFFFF);
    IO_DELAY(WRITE_DELAY);
    IOWR_16DIRECT(ISP1761_BASE, Addr + 1, (data32 >> 16 )& 0xFFFF);    
    IO_DELAY(WRITE_DELAY);
#else   
    // 32-bits    
    // 0626_2008, richard, IO_DELAY(WRITE_DELAY);
    IOWR(ISP1761_SLAVE_BASE, Addr, data32);
#endif    
}


alt_u32 HAL1761_RegRead32(alt_u32 Addr){
    alt_u32 data32;

#ifdef DATA_BUS_16BIT_WIDTH  
    alt_u16 high_word, low_word;
    low_word = IORD_16DIRECT(ISP1761_BASE, Addr  );
    IO_DELAY(READ_DELAY);
    high_word = IORD_16DIRECT(ISP1761_BASE, (Addr+1) );  
    IO_DELAY(READ_DELAY);
    data32 = (high_word << 16) | low_word;
#else    
    // 32-bits 
    // 0626_2008, richard, IO_DELAY(READ_DELAY);    
    data32 = IORD(ISP1761_SLAVE_BASE, Addr);
#endif  //DATA_BUS_16BIT_WIDTH
    return data32;
    
}

void HAL1761_DeviceDataRead(alt_u32 DataPort, alt_u8 szData[], alt_u32 ByteLen){
    alt_u32 data32;
    int i= 0, k = 4;
    while(i < ByteLen){
        data32 = IORD(ISP1761_SLAVE_BASE, DataPort);
        if (ByteLen - i < 4)
            k = ByteLen - i;
        memcpy(szData+i, &data32, k);
        i = i + 4;
    }        
}   

void HAL1761_DeviceDataWrite(alt_u32 DataPort, alt_u8 szData[], alt_u32 ByteLen){
    alt_u32 data32;
    int i= 0, k = 4;
    while(i < ByteLen){
        if (ByteLen - i < 4)
            k = ByteLen - i;
        memcpy(&data32, szData+i, k);
        IOWR(ISP1761_SLAVE_BASE, DataPort, data32);
        i = i + k;
    }        
}  

/*
void HAL1761_RegWrite16(alt_u32 Addr, alt_u16 data16){
    IO_DELAY(WRITE_DELAY);
    IOWR_16DIRECT(ISP1761_SLAVE_BASE, Addr, data16);
}

alt_u16 HAL1761_RegRead16(alt_u32 Addr){
    alt_u32 data16;

    // 32-bits 
    IO_DELAY(READ_DELAY);    
    data16 = IORD_16DIRECT(ISP1761_SLAVE_BASE, Addr);

    return data16;
    
}*/

#ifdef HCD_CONFIG_DMA
    // Memory Access by DMA
void HAL1761_MemWrite(alt_u32 Addr, alt_u32 szData[], alt_u32 ByteLen){
    int i;
    alt_u32 MemAddr = Addr & 0xFFFF;
    IO_DELAY(WRITE_DELAY);       

    for(i=0;i<ByteLen;i+=4){
        //HAL1761_Write32(MemAddr, *szData++);
        IOWR(ISP1761_SLAVE_BASE, MemAddr, *szData++);
        // it seems not necessary, HAL1761_Write32(0x033C, Addr);
        //Addr +=4;    
        MemAddr += 4;
    }
 
}

void HAL1761_MemRead(alt_u32 Addr, alt_u32 szData[], alt_u32 ByteLen){
    /*initialize the Register 0x33C-used to manage Multiple threads */
    // write it before first read
    alt_32 ISP1761_DMA_BASE = 0;
    bool bDone;
    alt_32 DmaConfig, Data32, time_start;

    // Config ISP1761 DMA
    // DMA_READ, DMA_ENALBE, BURST_LENG = 16-cycle DMA burst    
    DmaConfig = (ByteLen << 8) | (0x03 << 2) | 0x02 | 0x01;  
    
    alt_u32 MemAddr = Addr & 0xFFFF;
    HAL1761_RegWrite32(0x033C, Addr);
    HAL1761_RegWrite32(0x0344 /* HC_DMA_START_ADDRESS_REG */, MemAddr);
    HAL1761_RegWrite32(0x0330 /* HC_DMACONFIG_REG */, DmaConfig);
    
    // CONFIG Controller DMA
    IOWR(ISP1761_DMA_BASE, 0, (alt_u32)szData);  // system start address (byte-alignment) 
    IOWR(ISP1761_DMA_BASE, 1, ByteLen);  // DMA lenght (unit in byte) 
    IOWR(ISP1761_DMA_BASE, 2, 0x01);  // start DMA
    
    // polling DMA status
    bDone = FALSE;
    time_start = alt_nticks();
    do{
        Data32 = IORD(ISP1761_DMA_BASE, 2);
        if (Data32 & 0x01){
            if ((alt_nticks() - time_start) > alt_ticks_per_second()){
                bDone = TRUE; // timeout
                DEBUG_ERR(("DMA Read fail\n"));
            }    
        }else{
            bDone = TRUE;
        }
    }while(!bDone);
    
    // disable dma
    HAL1761_RegWrite32(0x0330, 0);
    
     
}

#else
    // memory access by Programming IO (use CPU)

void HAL1761_MemWrite(alt_u32 Addr, alt_u32 szData[], alt_u32 ByteLen){
    int i;
    alt_u32 MemAddr = Addr & 0xFFFF;
    IO_DELAY(WRITE_DELAY);       
#if 0    
    memcpy((void *)ISP1761_SLAVE_BASE+MemAddr, szData, ByteLen); // data cached enabled
#else
    for(i=0;i<ByteLen;i+=4){
        //HAL1761_Write32(MemAddr, *szData++);
        IOWR(ISP1761_SLAVE_BASE, MemAddr, *szData++);
        // it seems not necessary, HAL1761_Write32(0x033C, Addr);
        //Addr +=4;    
        MemAddr += 4;
    }
#endif    
}

void HAL1761_MemRead(alt_u32 Addr, alt_u32 szData[], alt_u32 ByteLen){
    /*initialize the Register 0x33C-used to manage Multiple threads */
    // write it before first read
    int i;
    alt_u32 MemAddr = Addr & 0xFFFF;
    HAL1761_RegWrite32(0x033C, Addr);
    IO_DELAY(READ_DELAY);   
    
#if 0    
    // setup first data's address (pre-fatch)
    memcpy(szData, (void *)ISP1761_SLAVE_BASE+MemAddr, ByteLen); // data cached enabled
#else
    for(i=0;i<ByteLen;i+=4){
        //*szData++ = HAL1761_Read32(MemAddr);
        *szData++ = IORD(ISP1761_SLAVE_BASE, MemAddr);
        MemAddr += 4;
    }
#endif       
}

#endif


bool HAL1761_Init(void){
    alt_u32 msc1;
    
    
    /* Let's Play with Read Write Pulse width */
    /*this code is for increasing read pulse width */
    msc1 = HAL1761_RegRead32(0x20);
    DEBUG_OUT(("msc1 before= 0x%08lX\n", msc1));
    //Krishan, dma mode*/
    msc1 &= 0xFFFF7444;
    msc1 |= 0x00007444;
    HAL1761_RegWrite32(0x20, msc1);
    msc1 = HAL1761_RegRead32(0x20);
    DEBUG_OUT(("msc1 after write= 0x%08lX\n", msc1));
    
    return TRUE;    
        
}

void HAL1761_UnInit(void){
}


//int gnLoopPerUs=0;
void OS_udelay(int us){
#if 1
    usleep(us);
#else    
    int i=0, cnt = us << 3 ;
    while(i++ < cnt);
#endif    
}

void OS_mdelay(int ms){
    OS_udelay(ms*1000);
}