// --------------------------------------------------------------------
// Copyright (c) 2007 by Terasic Technologies Inc. 
// --------------------------------------------------------------------
//
// Permission:
//
//   Terasic grants permission to use and modify this code for use
//   in synthesis for all Terasic Development Boards and Altera Development 
//   Kits made by Terasic.  Other use of this code, including the selling 
//   ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL/Verilog or C/C++ source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Terasic provides no warranty regarding the use 
//   or functionality of this code.
//
// --------------------------------------------------------------------
//           
//                     Terasic Technologies Inc
//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
//                     HsinChu County, Taiwan
//                     302
//
//                     web: http://www.terasic.com/
//                     email: support@terasic.com
//
// --------------------------------------------------------------------
// Author: Richard Chang

#ifndef ISP1761_HOST_REGISTER_H_
#define ISP1761_HOST_REGISTER_H_


/* Registers accessed by Interface functions */
/***** HC Registers *****/

#define     HC_REVISION_REG         0x00    /* 8-31Revision Register (read only) */
#define     HC_CAPABILITY_REG       0x00    /* 0-7 Capability Register (read only) */

#define     HC_SPARAMS_REG          0x04    /* Structural Parameters Register */
#define     HC_CPARAMS_REG          0x08    /* Capability Parameters Register */

#define     HC_SP_PORTROUTE1_REG    0x0C    /* Companion Port Route Register 1 */
#define     HC_SP_PORTROUTE2_REG    0x10    /* Companion Port Route Register 1 */
#define     HC_USBCMD_REG           0x20    /* USB Command Register */
#define     HC_USBSTS_REG           0x24    /* USB Status Register */
#define     HC_INTERRUPT_REG_EHCI   0x28    /* INterrupt Enable Register */
#define     HC_FRINDEX_REG          0x2C    /* Frame Index Register */

//RR#define     HC_CTRLDSSEGMENT_REG    0x30    /* 4G Segment Selector Register (Only for 64bit)*/
//RR#define     HC_PERIODICBASE_REG     0x34    /* Periodic List Base Address Register */
//RR#define     HC_ASYNCLISTADDR_REG    0x38    /* Next Asynchronous List register */
#define     HC_CONFIGFLAG_REG       0x60    /* Conigured Flag  Register */

#define     HC_PORTSC1_REG      0x64    /* Port Status Control for Port1 */
#define     HC_PORTSC2_REG      0x68    /* Port Status Control for Port2 */
#define     HC_PORTSC3_REG      0x6C    /* Port Status Control for Port3 */
#define     HC_PORTSC4_REG      0x70    /* Port Status Control for Port4 */

//ISO Transfer Registers
#define     HC_ISO_PTD_DONEMAP_REG          0x130   /* ISO PTD Done Map Register */
#define     HC_ISO_PTD_SKIPMAP_REG          0x134   /* ISO PTD Skip Map Register */
#define     HC_ISO_PTD_LASTPTD_REG          0x138   /* ISO PTD Last PTD Register */

//INT Transfer Registers
#define     HC_INT_PTD_DONEMAP_REG          0x140   /* INT PTD Done Map Register */
#define     HC_INT_PTD_SKIPMAP_REG          0x144   /* INT PTD Skip Map Register */
#define     HC_INT_PTD_LASTPTD_REG          0x148   /* INT PTD Last PTD Register  */

//ATL Transfer Registers
#define     HC_ATL_PTD_DONEMAP_REG          0x150   /* ATL PTD Last PTD Register  */
#define     HC_ATL_PTD_SKIPMAP_REG          0x154   /* ATL PTD Last PTD Register  */
#define     HC_ATL_PTD_LASTPTD_REG          0x158   /* ATL PTD Last PTD Register  */

//RR#define     HC_ATL_PTDDONE_THRESHOLDCNT_REG         0x350   /* Revision Register (read only) */
//RR#define     HC_ATL_PTDDONE_THRESHOLDTIMEOUT_REG     0x351   /* Control Register */



//General Purpose Registers
#define     HC_CHIP_ID_REG          0x304   /* Chip ID Register */
#define     HC_SCRATCH_REG          0x308   /* Scratch Register */
#define     HC_RESET_REG            0x30C   /* HC Reset Register */
                                           
//Interrupt Registers
#define     HC_INTERRUPT_REG            0x310   /* Interrupt Register */
#define     HC_INTENABLE_REG            0x314   /* Interrupt enable Register */
#define     HC_ISO_IRQ_MASK_OR_REG      0x318   /* ISO Mask OR Register */
#define     HC_INT_IRQ_MASK_OR_REG      0x31C   /* INT Mask OR Register*/
#define     HC_ATL_IRQ_MASK_OR_REG      0x320   /* ATL Mask OR Register */
#define     HC_ISO_IRQ_MASK_AND_REG     0x324   /* ISO Mask AND Register */
#define     HC_INT_IRQ_MASK_AND_REG     0x328   /* INT Mask AND Register */
#define     HC_ATL_IRQ_MASK_AND_REG     0x32C   /* ATL Mask AND Register */

//RAM Registers
#define     HC_DMACONFIG_REG            0x330   /* DMA Config Register */
//RR#define     HC_TRANS_COUNT_REG          0x334   /* Transfer Counter Register */
//RR#define     HC_BUFFER_STAT_REG          0x338   /* Buffer status Register */
#define     HC_MEM_READ_REG             0x33C   /* Memory Register */

/*interrupt count and buffer status register*/

#define      HC_BUFFER_STATUS_REG       0x334
#define      HC_INT_THRESHOLD_REG       0x340 
#define      HC_DMA_START_ADDRESS_REG   0x344


/* HC Registers Bit positions definitions */

/* HC_HW_CNFG_REG (16 bit) */
#define     HC_GlOBALINT_ENABLE     0x0001      /* Bit 0    */
#define     HC_INT_EDGE_TRIGGER     0x0002      /* Bit 1    */
#define     HC_INT_ACTIVE_HIGH      0x0004      /* Bit 2    */
#define     HC_DREQ_POLARITY_HIGH   0x0020      /* Bit 5    */
#define     HC_DACK_POLARITY_HIGH   0x0040      /* Bit 6    */
#define     HC_EOT_POLARITY_HIGH    0x0080      /* Bit 7    */

#define     HC_SOF_INT              (1<< 0)
#define     HC_MSEC_INT             (1 << 1)
#define     HC_EOT_INT              (1 << 3)       /* Bit 3: End of transfer int.*/
#define     HC_INTL_INT             (1 << 7)
#define     HC_ATL_INT              (1 << 8)
#define     HC_ISO_INT              (1 << 9)

#endif /*ISP1761_HOST_REGISTER_H_*/