/* system.h
 *
 * Machine generated for a CPU named "cpu" as defined in:
 * d:\NIOS_II\DE3_Q80\DE3_DDR2\DE3_DDR2_150\software\DDR2_TEST_syslib\..\..\DE3_SOPC.ptf
 *
 * Generated: 2008-09-10 21:07:40.542
 *
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/*

DO NOT MODIFY THIS FILE

   Changing this file will have subtle consequences
   which will almost certainly lead to a nonfunctioning
   system. If you do modify this file, be aware that your
   changes will be overwritten and lost when this file
   is generated again.

DO NOT MODIFY THIS FILE

*/

/******************************************************************************
*                                                                             *
* License Agreement                                                           *
*                                                                             *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
* All rights reserved.                                                        *
*                                                                             *
* Permission is hereby granted, free of charge, to any person obtaining a     *
* copy of this software and associated documentation files (the "Software"),  *
* to deal in the Software without restriction, including without limitation   *
* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
* and/or sell copies of the Software, and to permit persons to whom the       *
* Software is furnished to do so, subject to the following conditions:        *
*                                                                             *
* The above copyright notice and this permission notice shall be included in  *
* all copies or substantial portions of the Software.                         *
*                                                                             *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
* DEALINGS IN THE SOFTWARE.                                                   *
*                                                                             *
* This agreement shall be governed in all respects by the laws of the State   *
* of California and by the laws of the United States of America.              *
*                                                                             *
******************************************************************************/

/*
 * system configuration
 *
 */

#define ALT_SYSTEM_NAME "DE3_SOPC"
#define ALT_CPU_NAME "cpu"
#define ALT_CPU_ARCHITECTURE "altera_nios2"
#define ALT_DEVICE_FAMILY "STRATIXIII"
#define ALT_STDIN "/dev/jtag_uart"
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN_BASE 0x10000068
#define ALT_STDIN_DEV jtag_uart
#define ALT_STDIN_PRESENT
#define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT_BASE 0x10000068
#define ALT_STDOUT_DEV jtag_uart
#define ALT_STDOUT_PRESENT
#define ALT_STDERR "/dev/jtag_uart"
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDERR_BASE 0x10000068
#define ALT_STDERR_DEV jtag_uart
#define ALT_STDERR_PRESENT
#define ALT_CPU_FREQ 133333499
#define ALT_IRQ_BASE NULL

/*
 * processor configuration
 *
 */

#define NIOS2_CPU_IMPLEMENTATION "fast"
#define NIOS2_BIG_ENDIAN 0

#define NIOS2_ICACHE_SIZE 4096
#define NIOS2_DCACHE_SIZE 2048
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_DCACHE_LINE_SIZE 32
#define NIOS2_DCACHE_LINE_SIZE_LOG2 5
#define NIOS2_FLUSHDA_SUPPORTED

#define NIOS2_EXCEPTION_ADDR 0x11020020
#define NIOS2_RESET_ADDR 0x11020000
#define NIOS2_BREAK_ADDR 0x11040820

#define NIOS2_HAS_DEBUG_STUB

#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0

/*
 * A define for each class of peripheral
 *
 */

#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_SYSID
#define __ALTERA_AVALON_TIMER
#define __DDR2_HIGH_PERF
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_PLL
#define __ALTERA_AVALON_CLOCK_CROSSING

/*
 * jtag_uart configuration
 *
 */

#define JTAG_UART_NAME "/dev/jtag_uart"
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_BASE 0x10000068
#define JTAG_UART_SPAN 8
#define JTAG_UART_IRQ 0
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_READ_CHAR_STREAM ""
#define JTAG_UART_SHOWASCII 1
#define JTAG_UART_READ_LE 0
#define JTAG_UART_WRITE_LE 0
#define JTAG_UART_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0
#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart

/*
 * onchip_mem configuration
 *
 */

#define ONCHIP_MEM_NAME "/dev/onchip_mem"
#define ONCHIP_MEM_TYPE "altera_avalon_onchip_memory2"
#define ONCHIP_MEM_BASE 0x11020000
#define ONCHIP_MEM_SPAN 131072
#define ONCHIP_MEM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define ONCHIP_MEM_RAM_BLOCK_TYPE "AUTO"
#define ONCHIP_MEM_INIT_CONTENTS_FILE "onchip_mem"
#define ONCHIP_MEM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define ONCHIP_MEM_GUI_RAM_BLOCK_TYPE "Automatic"
#define ONCHIP_MEM_WRITEABLE 1
#define ONCHIP_MEM_DUAL_PORT 0
#define ONCHIP_MEM_SIZE_VALUE 131072
#define ONCHIP_MEM_SIZE_MULTIPLE 1
#define ONCHIP_MEM_USE_SHALLOW_MEM_BLOCKS 0
#define ONCHIP_MEM_INIT_MEM_CONTENT 1
#define ONCHIP_MEM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define ONCHIP_MEM_INSTANCE_ID "NONE"
#define ONCHIP_MEM_READ_DURING_WRITE_MODE "DONT_CARE"
#define ONCHIP_MEM_IGNORE_AUTO_BLOCK_TYPE_ASSIGNMENT 1
#define ONCHIP_MEM_CONTENTS_INFO ""
#define ALT_MODULE_CLASS_onchip_mem altera_avalon_onchip_memory2

/*
 * sysid configuration
 *
 */

#define SYSID_NAME "/dev/sysid"
#define SYSID_TYPE "altera_avalon_sysid"
#define SYSID_BASE 0x10000060
#define SYSID_SPAN 8
#define SYSID_ID 1677202188u
#define SYSID_TIMESTAMP 1221051928u
#define SYSID_REGENERATE_VALUES 0
#define ALT_MODULE_CLASS_sysid altera_avalon_sysid

/*
 * timer configuration
 *
 */

#define TIMER_NAME "/dev/timer"
#define TIMER_TYPE "altera_avalon_timer"
#define TIMER_BASE 0x10000000
#define TIMER_SPAN 32
#define TIMER_IRQ 1
#define TIMER_ALWAYS_RUN 0
#define TIMER_FIXED_PERIOD 0
#define TIMER_SNAPSHOT 1
#define TIMER_PERIOD 1
#define TIMER_PERIOD_UNITS "ms"
#define TIMER_RESET_OUTPUT 0
#define TIMER_TIMEOUT_PULSE_OUTPUT 0
#define TIMER_LOAD_VALUE 19999
#define TIMER_COUNTER_SIZE 32
#define TIMER_MULT 0.0010
#define TIMER_TICKS_PER_SEC 1000
#define TIMER_FREQ 20000000
#define ALT_MODULE_CLASS_timer altera_avalon_timer

/*
 * altmemddr configuration
 *
 */

#define ALTMEMDDR_NAME "/dev/altmemddr"
#define ALTMEMDDR_TYPE "ddr2_high_perf"
#define ALTMEMDDR_BASE 0x00000000
#define ALTMEMDDR_SPAN 268435456
#define ALTMEMDDR_DEVICE_FAMILY "Stratix III"
#define ALTMEMDDR_DATAWIDTH 64
#define ALTMEMDDR_MEMTYPE "DDR2 SDRAM"
#define ALTMEMDDR_LOCAL_BURST_LENGTH 1
#define ALTMEMDDR_NUM_CHIPSELECTS 1
#define ALTMEMDDR_CAS_LATENCY 5.0
#define ALTMEMDDR_ADDR_WIDTH 23
#define ALTMEMDDR_BA_WIDTH 2
#define ALTMEMDDR_ROW_WIDTH 13
#define ALTMEMDDR_COL_WIDTH 10
#define ALTMEMDDR_CLOCKSPEED 3749
#define ALTMEMDDR_DATA_WIDTH_RATIO 4
#define ALTMEMDDR_REG_DIMM "false"
#define ALTMEMDDR_DQ_PER_DQS 8
#define ALT_MODULE_CLASS_altmemddr ddr2_high_perf

/*
 * ddr2_i2c_scl configuration
 *
 */

#define DDR2_I2C_SCL_NAME "/dev/ddr2_i2c_scl"
#define DDR2_I2C_SCL_TYPE "altera_avalon_pio"
#define DDR2_I2C_SCL_BASE 0x10000020
#define DDR2_I2C_SCL_SPAN 16
#define DDR2_I2C_SCL_DO_TEST_BENCH_WIRING 0
#define DDR2_I2C_SCL_DRIVEN_SIM_VALUE 0
#define DDR2_I2C_SCL_HAS_TRI 0
#define DDR2_I2C_SCL_HAS_OUT 1
#define DDR2_I2C_SCL_HAS_IN 0
#define DDR2_I2C_SCL_CAPTURE 0
#define DDR2_I2C_SCL_DATA_WIDTH 1
#define DDR2_I2C_SCL_RESET_VALUE 0
#define DDR2_I2C_SCL_EDGE_TYPE "NONE"
#define DDR2_I2C_SCL_IRQ_TYPE "NONE"
#define DDR2_I2C_SCL_BIT_CLEARING_EDGE_REGISTER 0
#define DDR2_I2C_SCL_FREQ 20000000
#define ALT_MODULE_CLASS_ddr2_i2c_scl altera_avalon_pio

/*
 * ddr2_i2c_sda configuration
 *
 */

#define DDR2_I2C_SDA_NAME "/dev/ddr2_i2c_sda"
#define DDR2_I2C_SDA_TYPE "altera_avalon_pio"
#define DDR2_I2C_SDA_BASE 0x10000030
#define DDR2_I2C_SDA_SPAN 16
#define DDR2_I2C_SDA_DO_TEST_BENCH_WIRING 0
#define DDR2_I2C_SDA_DRIVEN_SIM_VALUE 0
#define DDR2_I2C_SDA_HAS_TRI 1
#define DDR2_I2C_SDA_HAS_OUT 0
#define DDR2_I2C_SDA_HAS_IN 0
#define DDR2_I2C_SDA_CAPTURE 0
#define DDR2_I2C_SDA_DATA_WIDTH 1
#define DDR2_I2C_SDA_RESET_VALUE 0
#define DDR2_I2C_SDA_EDGE_TYPE "NONE"
#define DDR2_I2C_SDA_IRQ_TYPE "NONE"
#define DDR2_I2C_SDA_BIT_CLEARING_EDGE_REGISTER 0
#define DDR2_I2C_SDA_FREQ 20000000
#define ALT_MODULE_CLASS_ddr2_i2c_sda altera_avalon_pio

/*
 * pio_led configuration
 *
 */

#define PIO_LED_NAME "/dev/pio_led"
#define PIO_LED_TYPE "altera_avalon_pio"
#define PIO_LED_BASE 0x10000050
#define PIO_LED_SPAN 16
#define PIO_LED_DO_TEST_BENCH_WIRING 0
#define PIO_LED_DRIVEN_SIM_VALUE 0
#define PIO_LED_HAS_TRI 0
#define PIO_LED_HAS_OUT 1
#define PIO_LED_HAS_IN 0
#define PIO_LED_CAPTURE 0
#define PIO_LED_DATA_WIDTH 24
#define PIO_LED_RESET_VALUE 0
#define PIO_LED_EDGE_TYPE "NONE"
#define PIO_LED_IRQ_TYPE "NONE"
#define PIO_LED_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_LED_FREQ 20000000
#define ALT_MODULE_CLASS_pio_led altera_avalon_pio

/*
 * pio_button configuration
 *
 */

#define PIO_BUTTON_NAME "/dev/pio_button"
#define PIO_BUTTON_TYPE "altera_avalon_pio"
#define PIO_BUTTON_BASE 0x10000040
#define PIO_BUTTON_SPAN 16
#define PIO_BUTTON_DO_TEST_BENCH_WIRING 0
#define PIO_BUTTON_DRIVEN_SIM_VALUE 0
#define PIO_BUTTON_HAS_TRI 0
#define PIO_BUTTON_HAS_OUT 0
#define PIO_BUTTON_HAS_IN 1
#define PIO_BUTTON_CAPTURE 0
#define PIO_BUTTON_DATA_WIDTH 4
#define PIO_BUTTON_RESET_VALUE 0
#define PIO_BUTTON_EDGE_TYPE "NONE"
#define PIO_BUTTON_IRQ_TYPE "NONE"
#define PIO_BUTTON_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_BUTTON_FREQ 20000000
#define ALT_MODULE_CLASS_pio_button altera_avalon_pio

/*
 * pll configuration
 *
 */

#define PLL_NAME "/dev/pll"
#define PLL_TYPE "altera_avalon_pll"
#define PLL_BASE 0x11041000
#define PLL_SPAN 32
#define PLL_ARESET "None"
#define PLL_PFDENA "None"
#define PLL_LOCKED "None"
#define PLL_PLLENA "None"
#define PLL_SCANCLK "None"
#define PLL_SCANDATA "None"
#define PLL_SCANREAD "None"
#define PLL_SCANWRITE "None"
#define PLL_SCANCLKENA "None"
#define PLL_SCANACLR "None"
#define PLL_SCANDATAOUT "None"
#define PLL_SCANDONE "None"
#define PLL_CONFIGUPDATE "None"
#define PLL_PHASECOUNTERSELECT "None"
#define PLL_PHASEDONE "None"
#define PLL_PHASEUPDOWN "None"
#define PLL_PHASESTEP "None"
#define PLL_CONFIG_DONE 0
#define ALT_MODULE_CLASS_pll altera_avalon_pll

/*
 * clock_crossing_bridge configuration
 *
 */

#define CLOCK_CROSSING_BRIDGE_NAME "/dev/clock_crossing_bridge"
#define CLOCK_CROSSING_BRIDGE_TYPE "altera_avalon_clock_crossing"
#define CLOCK_CROSSING_BRIDGE_BASE 0x10000000
#define CLOCK_CROSSING_BRIDGE_SPAN 128
#define CLOCK_CROSSING_BRIDGE_UPSTREAM_FIFO_DEPTH 512
#define CLOCK_CROSSING_BRIDGE_DOWNSTREAM_FIFO_DEPTH 32
#define CLOCK_CROSSING_BRIDGE_DATA_WIDTH 32
#define CLOCK_CROSSING_BRIDGE_NATIVE_ADDRESS_WIDTH 5
#define CLOCK_CROSSING_BRIDGE_USE_BYTE_ENABLE 1
#define CLOCK_CROSSING_BRIDGE_USE_BURST_COUNT 0
#define CLOCK_CROSSING_BRIDGE_MAXIMUM_BURST_SIZE 8
#define CLOCK_CROSSING_BRIDGE_UPSTREAM_USE_REGISTER 0
#define CLOCK_CROSSING_BRIDGE_DOWNSTREAM_USE_REGISTER 0
#define CLOCK_CROSSING_BRIDGE_DEVICE_FAMILY "STRATIXIII"
#define ALT_MODULE_CLASS_clock_crossing_bridge altera_avalon_clock_crossing

/*
 * system library configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK TIMER
#define ALT_TIMESTAMP_CLK none

/*
 * Devices associated with code sections.
 *
 */

#define ALT_TEXT_DEVICE       ONCHIP_MEM
#define ALT_RODATA_DEVICE     ONCHIP_MEM
#define ALT_RWDATA_DEVICE     ONCHIP_MEM
#define ALT_EXCEPTIONS_DEVICE ONCHIP_MEM
#define ALT_RESET_DEVICE      ONCHIP_MEM

/*
 * The text section is initialised so no bootloader will be required.
 * Set a variable to tell crt0.S to provide code at the reset address and
 * to initialise rwdata if appropriate.
 */

#define ALT_NO_BOOTLOADER


#endif /* __SYSTEM_H_ */