Generation Report - DDR2 SDRAM High Performance Controller v8.0 |
|
| Entity Name | altmemddr_controller_phy | | Variation Name | altmemddr | | Variation HDL | Verilog HDL | | Output Directory | D:\NIOS_II\DE3_Q80\DE3_DDR2\DE3_DDR2_150 |
|
File SummaryThe MegaWizard interface is creating the following files in the output directory: |
| File | Description |
|---|
| altmemddr.v | A MegaCore® function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software. | | altmemddr.qip | Contains Quartus II project information for your MegaCore function variation. | | altmemddr.html | The MegaCore function report file. |
|
MegaCore Function Variation File Ports| Name | Direction | Width |
|---|
| local_address | INPUT | 23 | | local_write_req | INPUT | 1 | | local_read_req | INPUT | 1 | | local_burstbegin | INPUT | 1 | | local_ready | OUTPUT | 1 | | local_rdata | OUTPUT | 256 | | local_rdata_valid | OUTPUT | 1 | | local_wdata | INPUT | 256 | | local_be | INPUT | 32 | | local_size | INPUT | 1 | | reset_request_n | OUTPUT | 1 | | mem_odt | OUTPUT | 1 | | mem_clk | BIDIR | 2 | | mem_clk_n | BIDIR | 2 | | mem_cs_n | OUTPUT | 1 | | mem_cke | OUTPUT | 1 | | mem_addr | OUTPUT | 13 | | mem_ba | OUTPUT | 2 | | mem_ras_n | OUTPUT | 1 | | mem_cas_n | OUTPUT | 1 | | mem_we_n | OUTPUT | 1 | | mem_dq | BIDIR | 64 | | mem_dqs | BIDIR | 8 | | mem_dqsn | BIDIR | 8 | | mem_dm | OUTPUT | 8 | | local_refresh_ack | OUTPUT | 1 | | local_wdata_req | OUTPUT | 1 | | local_init_done | OUTPUT | 1 | | reset_phy_clk_n | OUTPUT | 1 | | oct_ctl_rs_value | INPUT | 14 | | oct_ctl_rt_value | INPUT | 14 | | global_reset_n | INPUT | 1 | | pll_ref_clk | INPUT | 1 | | phy_clk | OUTPUT | 1 | | aux_full_rate_clk | OUTPUT | 1 | | aux_half_rate_clk | OUTPUT | 1 | | soft_reset_n | INPUT | 1 |
|