// --------------------------------------------------------------------
// Copyright (c) 2007 by Terasic Technologies Inc. 
// --------------------------------------------------------------------
//
// Permission:
//
//   Terasic grants permission to use and modify this code for use
//   in synthesis for all Terasic Development Boards and Altera Development 
//   Kits made by Terasic.  Other use of this code, including the selling 
//   ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL/Verilog or C/C++ source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Terasic provides no warranty regarding the use 
//   or functionality of this code.
//
// --------------------------------------------------------------------
//           
//                     Terasic Technologies Inc
//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
//                     HsinChu County, Taiwan
//                     302
//
//                     web: http://www.terasic.com/
//                     email: support@terasic.com
//
// --------------------------------------------------------------------

#ifndef ISP1761_DEVICE_REGISTER_H_
#define ISP1761_DEVICE_REGISTER_H_

//============= register define ============
//
// initialization registers
#define DC_ADDRESS                  0x200
#define DC_MODE                     0x20C
#define DC_INT_CONFIG               0x210
#define DC_DEBUG                    0x212
#define DC_INT_ENABLE               0x214

//
// Data Flow Register
#define DC_EP_INDEX                 0x22C
#define DC_CONTROL_FUNC             0x228
#define DC_DATA_PORT                0x220
#define DC_BUF_LEN                  0x21C
#define DC_BUF_STATUS               0x21E
#define DC_EP_MAX_PK_SIZE           0x204
#define DC_EP_TYPE                  0x208

// DMA registger
#define DC_DMA_COMMAND              0x230
#define DC_DMA_TRANSFER_COUNTER     0x234
#define DC_DMA_CONFIG               0x238
#define DC_DMA_HARDWARE             0x23C
#define DC_DMA_INT_REASON           0x250
#define DC_DMA_INT_ENABLE           0x254
#define DC_DMA_EP                   0x258
#define DC_DMA_BURST_COUNTER        0x264


// General register
#define DC_INTERRUPT                0x218
#define DC_CHIP_ID                  0x270
#define DC_FRAME_NUMBER             0x274
#define DC_SCRATCH                  0x278
#define DC_UNLOCK_DEIVCE            0x27C
#define DC_INT_PULSE_WIDTH          0x280
#define DC_TEST_MODE                0x284

//======= bit define for register define =======
// Mode Register Bit define (DC_MODE, 0x20C)
#define MODE_SOFTCT                             0x00
#define MODE_WKUPCS                             0x04
#define MODE_GLINTENA                           0x08
#define MODE_SFRESET                            0x10
#define MODE_GOSUSP                             0x20
#define MODE_SNDRSU                             0x40
#define MODE_CLKAON                             0x80
#define DMA_CLKON                               0x200

// Addresss Register Bit define (DC_ADDRESS, 0x200)
#define ADDRESS_DEVICE_ENALBE                   0x80

//
#define DEFAULT_INT_PULSE_SIZE                  0x1E

// Interrupt config register bit difine (DC_INT_CONFIG, 0x210)
#define CONFIG_INTPOL_L                         0x00
#define CONFIG_INTPOL_H                         0x01
#define CONFIG_INTLVL_L                         0x00
#define CONFIG_INTLVL_P                         0x02
#define CONFIG_INT_DBG_OUTACK_NAK_NYET          0x00
#define CONFIG_INT_DBG_OUT_ACK_NYET             0x04
#define CONFIG_INT_DBG_OUT_ACK_NYET_FNAK        0x08
#define CONFIG_INT_DBG_IN_ACK_NAK               0x00
#define CONFIG_INT_DBG_IN_ACK                   0x10
#define CONFIG_INT_DBG_IN_ACK_FNAK              0x20
#define CONFIG_INT_DBG_ACK_NAK                  0x00
#define CONFIG_INT_DBG_ACK                      0x40
#define CONFIG_INT_ACK_FNAK                     0x80
#define DEFAULT_INT_CONFIG                      (CONFIG_INT_DBG_ACK |   CONFIG_INT_DBG_IN_ACK|  CONFIG_INT_DBG_OUT_ACK_NYET )    //0x54

// Interrupt enable register bit define (DC_INT_ENABLE, 0x214)
#define IE_RST                                  0x00000001
#define IE_SOF                                  0x00000002
#define IE_PSOF                                 0x00000004
#define IE_SUSP                                 0x00000008
#define IE_RESM                                 0x00000010
#define IE_HS_STA                               0x00000020
#define IE_DMA                                  0x00000040
#define IE_VBUS                                 0x00000080
#define IE_EP0SETUP                             0x00000100
#define IE_EP0RX                                0x00000400
#define IE_EP0TX                                0x00000800
#define IE_EP1RX                                0x00001000
#define IE_EP1TX                                0x00002000
#define IE_EP2RX                                0x00004000
#define IE_EP2TX                                0x00008000
#define IE_EP3RX                                0x00010000
#define IE_EP3TX                                0x00020000
#define IE_EP4RX                                0x00040000
#define IE_EP4TX                                0x00080000
#define IE_EP5RX                                0x00100000
#define IE_EP5TX                                0x00200000
#define IE_EP6RX                                0x00400000
#define IE_EP6TX                                0x00800000
#define IE_EP7RX                                0x01000000
#define IE_EP7TX                                0x02000000
#define IE_NON_CTRL_EP_MASK                     (IE_EP1RX | IE_EP1TX | IE_EP2RX | IE_EP2TX | IE_EP3RX | IE_EP3TX | IE_EP4RX | IE_EP4TX | IE_EP5RX | IE_EP5TX | IE_EP6RX | IE_EP6TX | IE_EP7RX | IE_EP7TX)
#define IE_BASIC_CTRL_EP_MASK                   (IE_EP0RX | IE_EP0TX | IE_EP0SETUP | IE_VBUS | IE_HS_STA | IE_SUSP |IE_RST | IE_RESM)

// Endpoint Index Register (DC_EP_INDEX) Bit define
#define EP0SETUP                                0x20
#define EP0RX                                   0x00
#define EP0TX                                   0x01
#define EP1RX                                   0x02
#define EP1TX                                   0x03
#define EP2RX                                   0x04
#define EP2TX                                   0x05
#define EP3RX                                   0x06
#define EP3TX                                   0x07
#define EP4RX                                   0x08
#define EP4TX                                   0x09
#define EP5RX                                   0x0a
#define EP5TX                                   0x0b
#define EP6RX                                   0x0c
#define EP6TX                                   0x0d
#define EP7RX                                   0x0e
#define EP7TX                                   0x0f 

// Control Function Register (DC_CONTROL_FUNC) Bit define
#define CONTROL_FUNC_STALL                      0x01
#define CONTROL_FUNC_STATUS_NAK                 0x00
#define CONTROL_FUNC_STATUS_EM_ACK              0x02
#define CONTROL_FUNC_VENDP                      0x08
#define CONTROL_FUNC_CLBUF                      0x10
#define CONTROL_FUNC_DSEN                       0x04

// Endpoint Type Register Bit Define (DC_EP_TYPE, 0x208)
#define EP_TYPE_ENDPTY_ISO                       0x0001
#define EP_TYPE_ENDPTY_BLK                       0x0002
#define EP_TYPE_ENDPTY_INT                       0x0003
#define EP_TYPE_DBLBUF                           0x0004
#define EP_TYPE_ENABLE                           0x0008
#define EP_TYPE_NOEMPKT                          0x0010

// Endpoint buffer status Register Bit Define (DC_BUF_STATUS, 0x21E)
#define NO_BUF_FILLED                           0x00
#define BUF0_FILLED                             0x01
#define BUF1_FILLED                             0x02
#define BUF1_AND_2_FILLED                       0x03

#endif /*ISP1761_DEVICE_REGISTER_H_*/