; Miscellaneous definitions VID0 EQU $000000 ; Video board select = 0 VID1 EQU $001000 ; Video board select = 1 CLK2 EQU $002000 ; Select bottom of clock driver board CLK3 EQU $003000 ; Select top of clock driver board CLK4 EQU $004000 ; Select DC bias board AD EQU $000001 ; Bit to start A/D conversion XFER EQU $000002 ; Bit to transfer A/D counts into the A/D FIFO CLK_ZERO EQU 0 ; Zero volts out on clock driver line SXMIT EQU $00F0E0 ; Transmit 8 pixels from two coadder boards ; Various delay parameters VP_DLY EQU $2C0000 ; Video delay time for 3 microsec/pixel VP_DLY_PT EQU $B80000 ; Pass through video delay time for 10.0 microsec/pixel DLY0 EQU $000000 ; null delay DLY1 EQU $B80000 ; LSYNC delay DLY2 EQU $B80000 ; LCLK1,2 delay ; Put all the waveform tables in SRAM IF @SCP("DOWNLOAD","HOST") ORG Y:$100,Y:$100 ; Download address ELSE ORG Y:$100,P:APL_NUM*N_W_APL+APL_LEN+$340 ; ROM address ENDIF ; Define switch state bits for CLK2 = bottom of clock board VCLK EQU 1 ; Fast clock LSYNC EQU 2 ; Line synchronization LCLK2 EQU 4 ; Line clock 2 LCLK1 EQU 8 ; Line clock 1 FSYNC EQU $10 ; Frame synchronization RESET EQU $20 ; Pixel reset clock READ EQU $40 ; Pixel read clock ; Copy of the clocking bit definition for easy reference ; DC CLK2+DLY1+FSYNC+LSYNC+VCLK+LCLK1+LCLK2+RESET+READ FRAME_INIT DC READ_ON-FRAME_INIT-2 DC CLK2+DLY1+FSYNC+LSYNC+0000+00000+LCLK2+00000+0000 DC CLK2+DLY1+00000+LSYNC+0000+00000+LCLK2+00000+0000 ;PULSE FSYNC LOW DC CLK2+DLY1+FSYNC+LSYNC+0000+00000+LCLK2+00000+0000 ;FSYNC HI READ_ON DC READ_OFF-READ_ON-2 DC CLK2+DLY1+FSYNC+LSYNC+0000+00000+LCLK2+00000+READ ; SET READ HI READ_OFF DC CLOCK_ROW-READ_OFF-2 DC CLK2+DLY1+FSYNC+LSYNC+0000+00000+LCLK2+00000+0000 ; SET READ LOW CLOCK_ROW DC CLOCK_ROW_RESET-CLOCK_ROW-2 DC CLK2+DLY1+FSYNC+00000+0000+00000+LCLK2+00000+0000 ;PULSE LSYNC LOW DC CLK2+DLY1+FSYNC+LSYNC+0000+00000+LCLK2+00000+0000 ;LSYNC HI DC CLK2+DLY1+FSYNC+LSYNC+VCLK+00000+LCLK2+00000+0000 ;PULSE VCLK HI DC CLK2+DLY1+FSYNC+LSYNC+0000+00000+LCLK2+00000+0000 ;VCLK LOW CLOCK_ROW_RESET DC CLOCK_COL_AND_READ_NO_XFER-CLOCK_ROW_RESET-2 DC CLK2+DLY1+FSYNC+00000+0000+00000+LCLK2+00000+0000 ;PULSE LSYNC LOW DC CLK2+DLY1+FSYNC+LSYNC+0000+00000+LCLK2+00000+0000 ;LSYNC HI DC CLK2+DLY1+FSYNC+LSYNC+VCLK+00000+LCLK2+00000+0000 ;PULSE VCLK HI DC CLK2+DLY1+FSYNC+LSYNC+0000+00000+LCLK2+00000+0000 ;VCLK LOW DC CLK2+DLY1+FSYNC+LSYNC+0000+00000+LCLK2+RESET+0000 ;PULSE RESET HI DC CLK2+DLY1+FSYNC+LSYNC+0000+00000+LCLK2+00000+0000 ;RESET LOW ; The first waveform table here does A/D conversion twice without writing ; The A/D values to the latch with XFER. The second waveform table does ; the A/D conversion and writes the previous 2 A/D values to the latch ; because of the pipeline delay in the ADS937 A/D converter. CLOCK_COL_AND_READ_NO_XFER DC END_CLOCK_COL_AND_READ_NO_XFER-CLOCK_COL_AND_READ_NO_XFER-2 DC CLK2+DLY2+FSYNC+LSYNC+0000+LCLK1+00000+00000+READ ; LCLK1 HI, LCLK2 LO DC CLK2+DLY2+FSYNC+LSYNC+0000+00000+LCLK2+00000+READ ; LCLK1 LO, LCLK2 HI DC VID0+VP_DLY+AD DC VID0 DC CLK2+DLY2+FSYNC+LSYNC+0000+LCLK1+00000+00000+READ ; LCLK1 HI, LCLK2 LO DC CLK2+DLY0+FSYNC+LSYNC+0000+00000+LCLK2+00000+READ ; LCLK1 LO, LCLK2 HI DC VID0+VP_DLY+AD DC VID0 END_CLOCK_COL_AND_READ_NO_XFER CLOCK_COL_AND_READ DC END_CLOCK_COL_AND_READ-CLOCK_COL_AND_READ-2 DC CLK2+DLY2+FSYNC+LSYNC+0000+LCLK1+00000+00000+READ ; LCLK1 HI, LCLK2 LO DC CLK2+DLY2+FSYNC+LSYNC+0000+00000+LCLK2+00000+READ ; LCLK1 LO, LCLK2 HI DC VID0+VP_DLY+AD+XFER DC VID0 DC CLK2+DLY2+FSYNC+LSYNC+0000+LCLK1+00000+00000+READ ; LCLK1 HI, LCLK2 LO DC CLK2+DLY2+FSYNC+LSYNC+0000+00000+LCLK2+00000+READ ; LCLK1 LO, LCLK2 HI DC VID0+VP_DLY+AD+XFER DC VID0 END_CLOCK_COL_AND_READ ; PT => Pass Through mode, wherein the coadder boards pass pixel data as ; quickly as possible to the timing board for transmission to the host ; same as non-pt, but with a different delay CLOCK_COL_AND_READ_PT_NO_XFER DC END_CLOCK_COL_AND_READ_PT_NO_XFER-CLOCK_COL_AND_READ_PT_NO_XFER-2 DC CLK2+DLY2+FSYNC+LSYNC+0000+LCLK1+00000+00000+READ ; LCLK1 HI, LCLK2 LO DC CLK2+DLY2+FSYNC+LSYNC+0000+00000+LCLK2+00000+READ ; LCLK1 LO, LCLK2 HI DC VID0+$100000+AD ; Delay needed for the DC VID0 ; coadder to get started DC VID0 DC CLK2+DLY2+FSYNC+LSYNC+0000+LCLK1+00000+00000+READ ; LCLK1 HI, LCLK2 LO DC CLK2+DLY2+FSYNC+LSYNC+0000+00000+LCLK2+00000+READ ; LCLK1 LO, LCLK2 HI DC VID0+$100000+AD DC VID0 DC VID0 END_CLOCK_COL_AND_READ_PT_NO_XFER CLOCK_COL_AND_READ_PT DC END_CLOCK_COL_AND_READ_PT-CLOCK_COL_AND_READ_PT-2 ; DC CLK2+DLY2+FSYNC+LSYNC+0000+LCLK1+00000+00000+READ ; LCLK1 HI, LCLK2 LO ; DC CLK2+DLY2+FSYNC+LSYNC+0000+00000+LCLK2+00000+READ ; LCLK1 LO, LCLK2 HI ; DC VID0+$100000+AD+XFER ; DC VID0 ; DC SXMIT ; DC CLK2+DLY2+FSYNC+LSYNC+0000+LCLK1+00000+00000+READ ; LCLK1 HI, LCLK2 LO ; DC CLK2+DLY2+FSYNC+LSYNC+0000+00000+LCLK2+00000+READ ; LCLK1 LO, LCLK2 HI ; DC VID0+$100000+AD+XFER ; DC VID0 DC SXMIT END_CLOCK_COL_AND_READ_PT ; These two waveforms tables only do A/D conversions and transfers of ; latched data to the FIFOs. They are executed once at the end of reading ; the array to get the two last A/D values left over because of the ; pipeline delay. READ_LAST_TWO_PIXELS DC SXMIT_LAST_TWO_PIXELS-READ_LAST_TWO_PIXELS-2 DC VID0+VP_DLY ; simply a delay, plus AD off DC VID0+VP_DLY ; simply a delay? DC VID0+AD+XFER ; AD on and transfer DC VID0+VP_DLY ; simply a delay, plus AD off DC VID0+VP_DLY ; simply a delay? DC VID0+AD+XFER ; AD on and transfer DC VID0+VP_DLY ; simply a delay, plus AD off SXMIT_LAST_TWO_PIXELS DC ZERO_BIASES-SXMIT_LAST_TWO_PIXELS-2 ; DC VID0+VP_DLY_PT ; simply a delay, plus AD off ; DC VID0+$100000+AD+XFER ; AD on and transfer ; DC VID0 ; AD off ; DC SXMIT ; transmit to host ; DC VID0+VP_DLY_PT ; simply a delay, plus AD off ; DC VID0+$100000+AD+XFER ; AD on and transfer ; DC VID0 ; AD off DC SXMIT ; transmit to host ; Zero out the DC biases during the power-on sequence (zero all lines) ZERO_BIASES DC CLOCKS-ZERO_BIASES-1 ; DC (CLK2<<8)+(0<<14)+CLK_ZERO ; DC (CLK2<<8)+(1<<14)+CLK_ZERO ; DC (CLK2<<8)+(2<<14)+CLK_ZERO ; DC (CLK2<<8)+(3<<14)+CLK_ZERO ; DC (CLK2<<8)+(4<<14)+CLK_ZERO ; DC (CLK2<<8)+(5<<14)+CLK_ZERO ; DC (CLK2<<8)+(6<<14)+CLK_ZERO ; DC (CLK2<<8)+(7<<14)+CLK_ZERO ; DC (CLK2<<8)+(8<<14)+CLK_ZERO ; DC (CLK2<<8)+(9<<14)+CLK_ZERO ; DC (CLK2<<8)+(10<<14)+CLK_ZERO ; DC (CLK2<<8)+(11<<14)+CLK_ZERO ; DC (CLK2<<8)+(12<<14)+CLK_ZERO ; DC (CLK2<<8)+(13<<14)+CLK_ZERO ; DC (CLK2<<8)+(14<<14)+CLK_ZERO ; DC (CLK2<<8)+(15<<14)+CLK_ZERO ; DC (CLK2<<8)+(16<<14)+CLK_ZERO ; DC (CLK2<<8)+(17<<14)+CLK_ZERO ; DC (CLK2<<8)+(18<<14)+CLK_ZERO ; DC (CLK2<<8)+(19<<14)+CLK_ZERO ; DC (CLK2<<8)+(20<<14)+CLK_ZERO ; DC (CLK2<<8)+(21<<14)+CLK_ZERO ; DC (CLK2<<8)+(22<<14)+CLK_ZERO ; DC (CLK2<<8)+(23<<14)+CLK_ZERO ; DC (CLK2<<8)+(24<<14)+CLK_ZERO ; DC (CLK2<<8)+(25<<14)+CLK_ZERO ; DC (CLK2<<8)+(26<<14)+CLK_ZERO ; DC (CLK2<<8)+(27<<14)+CLK_ZERO ; DC (CLK2<<8)+(28<<14)+CLK_ZERO ; DC (CLK2<<8)+(29<<14)+CLK_ZERO ; DC (CLK2<<8)+(30<<14)+CLK_ZERO ; DC (CLK2<<8)+(31<<14)+CLK_ZERO ; DC (CLK2<<8)+(32<<14)+CLK_ZERO ; DC (CLK2<<8)+(33<<14)+CLK_ZERO ; DC (CLK2<<8)+(34<<14)+CLK_ZERO ; DC (CLK2<<8)+(35<<14)+CLK_ZERO ; DC (CLK2<<8)+(36<<14)+CLK_ZERO ; DC (CLK2<<8)+(37<<14)+CLK_ZERO ; DC (CLK2<<8)+(38<<14)+CLK_ZERO ; DC (CLK2<<8)+(39<<14)+CLK_ZERO ; DC (CLK2<<8)+(40<<14)+CLK_ZERO ; DC (CLK2<<8)+(41<<14)+CLK_ZERO ; DC (CLK2<<8)+(42<<14)+CLK_ZERO ; DC (CLK2<<8)+(43<<14)+CLK_ZERO ; DC (CLK2<<8)+(44<<14)+CLK_ZERO ; DC (CLK2<<8)+(45<<14)+CLK_ZERO ; DC (CLK2<<8)+(46<<14)+CLK_ZERO ; DC (CLK2<<8)+(47<<14)+CLK_ZERO ; ; DC (CLK4<<8)+(0<<14)+CLK_ZERO ; DC (CLK4<<8)+(1<<14)+CLK_ZERO ; DC (CLK4<<8)+(2<<14)+CLK_ZERO ; DC (CLK4<<8)+(3<<14)+CLK_ZERO ; DC (CLK4<<8)+(4<<14)+CLK_ZERO ; DC (CLK4<<8)+(5<<14)+CLK_ZERO ; DC (CLK4<<8)+(6<<14)+CLK_ZERO ; DC (CLK4<<8)+(7<<14)+CLK_ZERO ; DC (CLK4<<8)+(8<<14)+CLK_ZERO ; DC (CLK4<<8)+(9<<14)+CLK_ZERO ; DC (CLK4<<8)+(10<<14)+CLK_ZERO ; DC (CLK4<<8)+(11<<14)+CLK_ZERO ; DC (CLK4<<8)+(12<<14)+CLK_ZERO ; DC (CLK4<<8)+(13<<14)+CLK_ZERO ; DC (CLK4<<8)+(14<<14)+CLK_ZERO ; DC (CLK4<<8)+(15<<14)+CLK_ZERO ; DC (CLK4<<8)+(16<<14)+CLK_ZERO ; DC (CLK4<<8)+(17<<14)+CLK_ZERO ; DC (CLK4<<8)+(18<<14)+CLK_ZERO ; DC (CLK4<<8)+(19<<14)+CLK_ZERO ; DC (CLK4<<8)+(20<<14)+CLK_ZERO ; DC (CLK4<<8)+(21<<14)+CLK_ZERO ; DC (CLK4<<8)+(22<<14)+CLK_ZERO ; DC (CLK4<<8)+(23<<14)+CLK_ZERO ; DC (CLK4<<8)+(24<<14)+CLK_ZERO ; DC (CLK4<<8)+(25<<14)+CLK_ZERO ; DC (CLK4<<8)+(26<<14)+CLK_ZERO ; DC (CLK4<<8)+(27<<14)+CLK_ZERO ; DC (CLK4<<8)+(28<<14)+CLK_ZERO ; DC (CLK4<<8)+(29<<14)+CLK_ZERO ; DC (CLK4<<8)+(30<<14)+CLK_ZERO ; DC (CLK4<<8)+(31<<14)+CLK_ZERO ; DC (CLK4<<8)+(32<<14)+CLK_ZERO ; DC (CLK4<<8)+(33<<14)+CLK_ZERO ; DC (CLK4<<8)+(34<<14)+CLK_ZERO ; DC (CLK4<<8)+(35<<14)+CLK_ZERO ; DC (CLK4<<8)+(36<<14)+CLK_ZERO ; DC (CLK4<<8)+(37<<14)+CLK_ZERO ; DC (CLK4<<8)+(38<<14)+CLK_ZERO ; DC (CLK4<<8)+(39<<14)+CLK_ZERO ; DC (CLK4<<8)+(40<<14)+CLK_ZERO ; DC (CLK4<<8)+(41<<14)+CLK_ZERO ; DC (CLK4<<8)+(42<<14)+CLK_ZERO ; DC (CLK4<<8)+(43<<14)+CLK_ZERO ; DC (CLK4<<8)+(44<<14)+CLK_ZERO ; DC (CLK4<<8)+(45<<14)+CLK_ZERO ; DC (CLK4<<8)+(46<<14)+CLK_ZERO ; DC (CLK4<<8)+(47<<14)+CLK_ZERO ; ; Initialize all DACs, starting with the clock driver ones CLOCKS DC BIASES-CLOCKS-1 ; Values for IR clock driver board. The clock driver board is jumpered for ; bipolar operation MAX_V EQU 7.5 ; Maximum voltage from bias driver board MAX_V2 EQU 15.0 ; 2 x MAX_V CLK_HI EQU 5.0 ; High Clock voltage CLK_LO EQU 0.0 ; Low Clock voltage ; Clocking voltages ; set voltages using CLK2 0-47, just as if setting biases on CLK4, but remember that ; switch states for output lines 0-11 are CLK2 and ; switch states for output lines 12-23 are CLK3 DC (CLK2<<8)+(0<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095) ; Pin #1, VCLK DC (CLK2<<8)+(1<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(2<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095) ; Pin #2, LSYNC DC (CLK2<<8)+(3<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(4<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095) ; Pin #3, LCLK2 DC (CLK2<<8)+(5<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(6<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095) ; Pin #4, LCLK1 DC (CLK2<<8)+(7<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(8<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095) ; Pin #5, FSYNC DC (CLK2<<8)+(9<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(10<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095) ; Pin #6, RESET DC (CLK2<<8)+(11<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(12<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095) ; Pin #7, READ DC (CLK2<<8)+(13<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095) ; HAWAII-1R DC bias voltage definition VDD EQU 5.0 ; Power supply VDDA EQU 5.0 ; Power supply BIASPOWER EQU 5.0 ; Power supply VSS EQU 0.0 ; Multiplexer ground MUXSUB EQU 0.0 ; Multiplexer ground DRAIN EQU 0.0 ; Output amp supply CELLDRAIN EQU 0.0 ; Output amp supply VRESET EQU 0.5 ; Detector reset voltage DSUB EQU 0.0 ; Detector common BIASGATE EQU 3.4 ; Sets SFD current ; DC Bias voltages assignments for the DC bias board. The DC bias board is strapped ; for bipolar outputs to accomodate the +1.0 volt VssOUT required for the video ; source followers. The rail voltage is MAX_V = 7.5 volts. MAX_V2 = 2 x MAX_V = 15.0 BIASES DC END_WAVEFORMS-BIASES-1 DC (CLK4<<8)+(1<<14)+@CVI((VDD+MAX_V)/MAX_V2*4095) ; pin #1 VDD DC (CLK4<<8)+(3<<14)+@CVI((VDDA+MAX_V)/MAX_V2*4095) ; pin #2 VDDA DC (CLK4<<8)+(5<<14)+@CVI((BIASPOWER+MAX_V)/MAX_V2*4095) ; pin #3 BIASPOWER DC (CLK4<<8)+(7<<14)+@CVI((VSS+MAX_V)/MAX_V2*4095) ; pin #4 VSS DC (CLK4<<8)+(9<<14)+@CVI((MUXSUB+MAX_V)/MAX_V2*4095) ; pin #5 MUXSUB DC (CLK4<<8)+(11<<14)+@CVI((DRAIN+MAX_V)/MAX_V2*4095) ; pin #6 DRAIN DC (CLK4<<8)+(13<<14)+@CVI((CELLDRAIN+MAX_V)/MAX_V2*4095) ; pin #7 CELLDRAIN DC (CLK4<<8)+(15<<14)+@CVI((VRESET+MAX_V)/MAX_V2*4095) ; pin #8 VRESET DC (CLK4<<8)+(17<<14)+@CVI((DSUB+MAX_V)/MAX_V2*4095) ; pin #9 DSUB DC (CLK4<<8)+(19<<14)+@CVI((BIASGATE+MAX_V)/MAX_V2*4095) ; pin #10 BIASGATE ; DAC settings for the video offsets with two coadder boards installed OFFSET EQU $000 OFFSET0 EQU OFFSET OFFSET1 EQU OFFSET OFFSET2 EQU OFFSET OFFSET3 EQU OFFSET OFFSET4 EQU OFFSET OFFSET5 EQU OFFSET OFFSET6 EQU OFFSET OFFSET7 EQU OFFSET OFF_0 DC $0c0000+OFFSET0 ; Input offset board #0, channel A coadder OFF_1 DC $0c4000+OFFSET1 ; Input offset board #0, channel B coadder OFF_2 DC $0c8000+OFFSET2 ; Input offset board #0, channel C coadder OFF_3 DC $0cc000+OFFSET3 ; Input offset board #0, channel D coadder OFF_4 DC $1c0000+OFFSET4 ; Input offset board #1, channel A coadder OFF_5 DC $1c4000+OFFSET5 ; Input offset board #1, channel B coadder OFF_6 DC $1c8000+OFFSET6 ; Input offset board #1, channel C coadder OFF_7 DC $1cc000+OFFSET7 ; Input offset board #1, channel D coadder END_WAVEFORMS