COMMENT *

This file is used to generate boot DSP code for the PCI interface board using
	a DSP56301 as its main processor.

This is Revision 1.4 DSP code.
	*
	PAGE    132     ; Printronix page width - 132 columns

; Equates to define the X: memory tables
VAR_TBL		EQU	0	; Variables and constants table
ARG_TBL		EQU	$30	; Command arguments and addresses
TIM_TBL		EQU	ARG_TBL+$30	; Readout timing parameters
TIM_LEN		EQU	$100	; Length of TIM_TBL = 256 bytes = 64 entries
SC_TBL		EQU	$100	; Scatter/Gather table
BUSY		EQU	0	; =1 if current block is being read or written
N_TABLE		EQU	255	; Number of entries in scatter/gather table
NRDFIFO		EQU	128	; Number of 512 pixel chunks in FIFO per 
				;   image block

; Various addressing control registers
BCR	EQU	$FFFFFB		; Bus Control Register
DCR	EQU	$FFFFFA		; DRAM Control Register
AAR0	EQU	$FFFFF9		; Address Attribute Register, channel 0	
AAR1	EQU	$FFFFF8		; Address Attribute Register, channel 1	
AAR2	EQU	$FFFFF7		; Address Attribute Register, channel 2	
AAR3	EQU	$FFFFF6		; Address Attribute Register, channel 3	
PCTL	EQU	$FFFFFD		; PLL control register
IPRP	EQU	$FFFFFE		; Interrupt Priority register - Peripheral
IPRC	EQU	$FFFFFF		; Interrupt Priority register - Core

; PCI control register
DTXS	EQU	$FFFFCD		; DSP Slave transmit data FIFO
DTXM	EQU	$FFFFCC		; DSP Master transmit data FIFO
DRXR	EQU	$FFFFCB		; DSP Receive data FIFO
DPSR	EQU	$FFFFCA		; DSP PCI Status Register 
DSR	EQU	$FFFFC9		; DSP Status Register
DPAR	EQU	$FFFFC8		; DSP PCI Address Register
DPMC	EQU	$FFFFC7		; DSP PCI Master Control Register 
DPCR	EQU	$FFFFC6		; DSP PCI Control Register
DCTR	EQU	$FFFFC5		; DSP Control Register

; Port E is the Synchronous Communications Interface (SCI) port
PCRE	EQU	$FFFF9F		; Port Control Register
PRRE	EQU	$FFFF9E		; Port Direction Register
PDRE	EQU	$FFFF9D		; Port Data Register

; Various PCI register bit equates
STRQ	EQU	1		; Slave transmit data request (DSR)
SRRQ	EQU	2		; Slave receive data request (DSR) 
HACT	EQU	23		; Host active, low true (DSR)
MTRQ	EQU	1		; Set whem master transmitter is not full (DPSR)
MARQ	EQU	4		; Master address request (DPSR)
TRTY	EQU	10		; PCI Target Retry (DPSR)

; The DCTR host flags are written by the DSP and read by PCI host
DCTR_RPLY  EQU	3		; Set after reply
DCTR_BUF0  EQU	4		; Set after buffer 0 is written to
DCTR_BUF1  EQU	5		; Set after buffer 1 is written to
INTA	   EQU	6		; Request PCI interrupt

; The DSR host flags are written by the PCI host and read by the DSP
DSR_BUF0   EQU	4		; PCI host sets this when copying buffer 0
DSR_BUF1   EQU	5		; PCI host sets this when copying buffer 1

; DPCR bit definitions
CLRT	EQU	14		; Clear transmitter
MACE	EQU	18		; Master access counter enable
IAE	EQU	21		; Insert Address Enable

; Addresses of ESSI port
TX00	EQU	$FFFFBC		; Transmit Data Register 0
SSISR0	EQU	$FFFFB7		; Status Register
CRB0	EQU	$FFFFB6		; Control Register B
CRA0	EQU	$FFFFB5		; Control Register A

; SSI Control Register A Bit Flags
TDE	EQU	6		; Set when transmitter data register is empty

; Miscellaneous addresses
RDFIFO	EQU	$FFFFFF		; Read the FIFO for incoming fiber optic data
TCSR0	EQU	$FFFF8F		; Triper timer control and status register 0
TCSR1	EQU	$FFFF8B		; Triper timer control and status register 1
TCSR2	EQU	$FFFF87		; Triper timer control and status register 2

; Phase Locked Loop initialization
PLL_INIT EQU	$750012		; PLL = 33 MHz x 19 / 8 = 78.4 MHz

; Port C is Enhanced Synchronous Serial Port 0
PCRC	EQU	$FFFFBF		; Port C Control Register
PRRC	EQU	$FFFFBE		; Port C Data direction Register
PDRC	EQU	$FFFFBD		; Port C GPIO Data Register

; Port D is Enhanced Synchronous Serial Port 1
PCRD	EQU	$FFFFAF		; Port D Control Register
PRRD	EQU	$FFFFAE		; Port D Data direction Register
PDRD	EQU	$FFFFAD		; Port D GPIO Data Register

; Bit number definitions of GPIO pins on Port C
ROM_FIFO EQU	2		; Select ROM or FIFO accesses for AA1

; Bit number definitions of GPIO pins on Port D
EF	EQU	0		; FIFO Empty flag, low true
HF	EQU	1		; FIFO half full flag, low true
RS	EQU	2		; FIFO reset signal, low true
FSYNC	EQU	3		; High during image transmission
MODE	EQU	4		; 1 for 32-bit reply data, 0 for 16-bit image
WRFIFO	EQU	5		; Low true if FIFO is being written to

; STATUS bit definitions
ODD_EVEN	EQU	0		; Block number 0 or 1 in image transfers
SCATTERING 	EQU	1		; Still Scattering the image if set
GATHERING 	EQU	2		; Still Gathering the image if set
RDI		EQU	3		; Set to start reading an image
DOWNLOAD_PCI	EQU	4		; Set to download PCI DSP code

; TIM_STAT = timing board status and configuration word
SHUTTER	EQU	11

; Special address for two words for the DSP to bootstrap code from the EEPROM
	IF	@SCP("DOWNLOAD","ROM")		; Boot from ROM on power-on
	ORG	P:0,P:0
	DC	END_ADR-INIT-2			; Number of boot words
	DC	INIT				; Starting address
	ORG	P:0,P:2
INIT	JMP	<INIT_PCI			; Configure PCI port
	NOP
	ENDIF

	IF	@SCP("DOWNLOAD","HOST")		; Download via host computer
	ORG	P:0,P:0
	DC	END_ADR-INIT-2			; Number of boot words
	DC	INIT				; Starting address
	ORG	P:0,P:2
INIT	JMP	<START
	NOP
	ENDIF

	IF	@SCP("DOWNLOAD","ONCE")		; Download via ONCE debugger
	ORG	P:0,P:0
INIT	JMP	<START
	NOP
	ENDIF

; Vectored interrupt table, addresses at the beginning are reserved
	DC	0,0,0,0,0,0,0,0,0,0,0,0,0,0	; $02-$0f Reserved
	DC	0,0				; $10-$13 Reserved
	JSR	SCATTER_FIFO			; $12 - IRQB = FIFO HF*
	JSR	CLEAN_UP_PCI			; $14 - Software reset switch
	DC	0,0,0,0,0,0,0,0,0,0		; Reserved interrupts
	DC	0,0,0,0,0,0,0,0,0,0,0,0,0,0
	JSR	DOWNLOAD_PCI_DSP_CODE		; $2F

; Now we're at P:$30, where some unused vector addresses are located

; This is ROM only code that is only executed once on power-up when the 
;   ROM code is downloaded. It is skipped over on OnCE or PCI downloads.
; Initialize the PLL - phase locked loop
INIT_PCI
	MOVEP	#PLL_INIT,X:PCTL	; Initialize PLL 
	NOP

; Program the PCI self-configuration registers
	MOVE 	#0,X0
	MOVEP	#$500000,X:DCTR		; Set self-configuration mode
	REP	#4
	MOVEP	X0,X:DPAR		; Dummy writes to configuration space
	MOVEP	#>$0000,X:DPMC		; Subsystem ID
	MOVEP	#>$0000,X:DPAR		; Subsystem Vendor ID

; PCI Personal reset
	MOVEP	X0,X:DCTR		; Personal software reset
	NOP
	NOP
	JSET	#HACT,X:DSR,*		; Test for personal reset completion
	MOVE	P:(*+3),X0		; Trick to write "JMP <START" to P:0
	MOVE	X0,P:(0)
	JMP	<START

DOWNLOAD_PCI_DSP_CODE
	BCLR	#IAE,X:DPCR		; Do not insert PCI address with data
DNL0	JCLR	#SRRQ,X:DSR,*		; Wait for a receiver word
	MOVEP	X:DRXR,A		; Read it
	CMP	#$555AAA,A		; Check for sanity header word
	JNE	<DNL0
	MOVE	OMR,A
	AND	#$FFFFF0,A
	OR	#$00000C,A
	NOP
	MOVE	A,OMR			; Set boot mode to $C = PCI
	JMP	$FF0000			; Jump to boot code internal to DSP

	DC	0,0,0,0,0,0,0,0,0,0,0,0			; Filler
	DC	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0	; $60-$71 Reserved PCI 

; Three non-maskable fast interrupt service routines for clearing PCI interrupts
	BCLR	#INTA,X:DCTR			; $73 - Clear PCI interrupt
	BCLR	#DCTR_RPLY,X:DCTR		; Clear reply interrupt bit
	BCLR	#INTA,X:DCTR			; $75 - Clear PCI interrupt
	BCLR	#DCTR_BUF0,X:DCTR		; Clear buffer 0 interrupt bit
	BCLR	#INTA,X:DCTR			; $77 - Clear PCI interrupt
	BCLR	#DCTR_BUF1,X:DCTR		; Clear buffer 1 interrupt bit

; Interrupt locations for host commands
	JSR	READ_CONTROLLER_STATUS		; $79
	JSR	WRITE_CONTROLLER_STATUS		; $7B
	JSR	RESET_CONTROLLER		; $7D
	JSR	LOAD_APPLICATION		; $7F
	JSR	CLEAN_UP_PCI			; $81
	JSR	READ_PCI_STATUS			; $83
	JSR	TEST_DATA_LINK			; $85
	JSR	READ_MEMORY			; $87
	JSR	WRITE_MEMORY			; $89
	JSR	READ_CONTROLLER_CONFIGURATION	; $8B
	JSR	POWER_ON			; $8D
	JSR	POWER_OFF			; $8F
	JSR	SET_BIAS_VOLTAGES		; $91
	JSR	CLEAR_ARRAY			; $93
	JSR	STOP_IDLE_MODE			; $95
	JSR	RESUME_IDLE_MODE		; $97
	JSR	READ_EXPOSURE_TIME		; $99
	JSR	START_EXPOSURE			; $9B 
	BSET	#RDI,X:<STATUS			; $9D - Read Image
	NOP	
	JSR	ABORT_READOUT			; $9F
	JSR	ABORT_EXPOSURE			; $A1
	JSR	PAUSE_EXPOSURE			; $A3
	JSR	RESUME_EXPOSURE			; $A5
	JSR	READ_ARRAY			; $A7
	JSR	OPEN_SHUTTER			; $A9
	JSR	CLOSE_SHUTTER			; $AB
	JSR	SET_ARRAY_TEMPERATURE		; $AD
	JSR	READ_ARRAY_TEMPERATURE		; $AF
						; $B1 to $FF - Available

START	MOVEP	#>$000001,X:DPMC
	BSET	#20,X:DCTR		; HI32 mode = 1 => PCI
	BCLR	#21,X:DCTR
	BCLR	#22,X:DCTR
	NOP
	BSET	#MACE,X:DPCR		; Master access counter enable
	BSET	#IAE,X:DPCR		; Insert PCI address before data
	NOP				; End of PCI programming

; Set operation mode register OMR to normal expanded
	MOVEC   #$0000,OMR	; Operating Mode Register = Normal Expanded
	MOVEC	#0,SP		; Reset the Stack Pointer SP

; Move the table of constants from P: space to X: space
	MOVE	#CONSTANTS_TBL_START,R1 	; Start of table of constants 
	MOVE	#2,R0				; Leave X:0 for STATUS
	DO	#CONSTANTS_TBL_LENGTH,L_WRITE
	MOVE	P:(R1)+,X0
	MOVE	X0,X:(R0)+			; Write the constants to X:
L_WRITE

; Program the serial port ESSI0 = Port C for serial transmission to 
;   the timing board
	MOVEP	#>0,X:PCRC	; Software reset of ESSI0
	MOVEP	#$000809,X:CRA0	; Divide 78.4 MHz by 20 to get 3.92 MHz
				; DC0-CD4 = 0 for non-network operation
				; WL0-WL2 = ALC = 0 for 2-bit data words
				; SSC1 = 0 for SC1 not used
	MOVEP	#$010120,X:CRB0	; SCKD = 1 for internally generated clock
				; SHFD = 0 for MSB shifted first
				; CKP = 0 for rising clock edge transitions
				; TE0 = 1 to enable transmitter #0
				; MOD = 0 for normal, non-networked mode
				; FSL1 = 1, FSL0 = 0 for on-demand transmit
	MOVEP	#%101000,X:PCRC	; Control Register (0 for GPIO, 1 for ESSI)
				; Set SCK0 = P3, STD0 = P5 to ESSI0
	MOVEP	#%010111,X:PRRC	; Data Direction Register (0 for In, 1 for Out)
	MOVEP	#%000101,X:PDRC	; Data Register - ROM/FIFO* = 0, SC02 = 0,
				;   AUX1 = 0, AUX2 = AUX3 = 1

; Conversion from software bits to schematic labels for Port C and D
;	PC0 = SC00 = AUX3		PD0 = SC10 = EF*
;	PC1 = SC01 = ROM/FIFO*		PD1 = SC11 = HF*
;	PC2 = SC02 = AUX2		PD2 = SC12 = RS*
;	PC3 = SCK0 = Serial clock	PD3 = SCK1 = FSYNC*
;	PC4 = SRD0 = AUX1		PD4 = SRD1 = MODE
;	PC5 = STD0 = Serial data	PD5 = STD1 = WRFIFO*

; Program the serial port ESSI1 = Port D for general purpose I/O (GPIO)
	MOVEP	#%000000,X:PCRD	; Control Register (0 for GPIO, 1 for ESSI)
	MOVEP	#%010100,X:PRRD	; Data Direction Register (0 for In, 1 for Out)
	MOVEP	#%010000,X:PDRD	; Data Register - Pulse RS* low, MODE = 1
	REP	#10
	NOP
	MOVEP	#%010100,X:PDRD

; Program the SCI port to benign values
	MOVEP	#%000,X:PCRE	; Port Control Register = GPIO
	MOVEP	#%110,X:PRRE	; Port Direction Register (0 = Input)
	MOVEP	#%110,X:PDRE	; Port Data Register
;	PE0 = RXD
;	PE1 = TXD
;	PE2 = SCLK

; Program the triple timer to assert TCI0 as an GPIO output = 1
	MOVEP	#$2800,X:TCSR0
	MOVEP	#$2800,X:TCSR1
	MOVEP	#$2800,X:TCSR2

; Program the AA1 pin to read the FIFO memory for incoming timing board data
	MOVEP	#$FFFC21,X:AAR1	; Y = $FFF000 to $FFFFFF asserts AA1 low true

; Program the DRAM memory access and addressing
	MOVEP	#$000020,X:BCR	; Bus Control Register
	MOVEP	#$893A05,X:DCR	; DRAM Control Register
	MOVEP	#$000122,X:AAR2	; Y: $000000 to $7FFFFF asserts AA2
	MOVEP	#$800122,X:AAR0	; Y: $800000 to $FFFFFF asserts AA0
	MOVEP	#$000112,X:AAR3	; X: $000000 to $7FFFFF asserts AA3

; Exercise the data lines a little to fill them with electrons
	MOVE	#$20000,R0
	MOVE	#15000000,X1
	MOVE	#$FFFFFF,X0
	DO	X1,INIT_DRAM
	MOVE	X0,Y:(R0)+
INIT_DRAM

; Initialize the fiber optic serial transmitter to zero
	JCLR	#TDE,X:SSISR0,*
	MOVEP	#$000000,X:TX00

; Clear out the PCI receiver and transmitter FIFOs
	BSET	#CLRT,X:DPCR		; Clear the transmitter
	JSET	#CLRT,X:DPCR,*		; Wait for the clearing to be complete	
CLR0	JCLR	#SRRQ,X:DSR,CLR1	; Wait for the receiver to be empty
	MOVEP	X:DRXR,X0		; Read receiver to empty it
	NOP
	JMP	<CLR0
CLR1

; Clear all PCI error conditions
	MOVEP	X:DPSR,A
	OR	#$1FE,A
	NOP
	MOVEP	A,X:DPSR

; Initialize the Scatter/Gather table to zero
	CLR	A
	MOVE	#X_TABLE,R0
	REP	#N_TABLE
	MOVE	A,X:(R0)+

; Only initialize STATUS and REPLY if booting from ROM after power-up
	IF	@SCP("DOWNLOAD","ROM")
	MOVE	A,X:<STATUS	; Initialize the STATUS variable
	MOVE	A,X:<REPLY	; Initialize the REPLY variable
	ENDIF

; Enable one interrupt only: software reset switch
	MOVEP	#$0001C0,X:IPRC	; IRQB priority = 1 (FIFO half full HF*)
				; IRQC priority = 2 (reset switch)
	MOVE	#$200,SR	; Mask set up for reset switch only

; Send a 'DON' reply after a download
	IF	@SCP("DOWNLOAD","HOST")
	JMP	<FINISH		; Write 'DON' to PCI board reply area
	ENDIF

; ************  Start of command interpreting code  ******************

; Test for fiber optic data on the FIFO. Discard the header for now

; Check for the header $AC in the first byte = X0. Wait a little while and
;  clear the FIFO if its not $AC - there was probably noise on the line.
; We assume only two word replies here - Header = (S,D,#words)  Reply

GET_FO	JCLR	#EF,X:PDRD,GET_RDI	; Test for new fiber optic data
	MOVEP	Y:RDFIFO,X0		; Read the first fiber optic word	
	MOVE	X:<C00FF00,A
	AND	X0,A
	CMP	#$00AC00,A		; First byte must be $AC = preamble
	JNE	<CHK_ERR
	MOVE	X:<C0000F8,A		; Source byte must be 7 or less
	AND	X0,A
	JNE	<CHK_ERR

; Now check the second word of the header for self-consistency
	REP	#10
	NOP
	MOVEP	Y:RDFIFO,X0		; Read the second fiber optic word
	MOVE	X:<C00FF00,A
	AND	X0,A
	JNE	<CHK_ERR		; Destination byte must be zero
	MOVE	X:<C0000F8,A
	AND	X0,A
	JNE	<CHK_ERR		; Number of words in command < 8

; Read the reply word from the fiber optics FIFO
	JSR	<GET_REPLY		; Move the FIFO reply into A1

; If its a good reply just write it to the PCI reply address
	JSR	<UNSQUASH		; Separate it into X0 and X1
	JMP	<FINISH1		; Write it to the PCI reply address

; There was an erroneous word on the fiber optic line -> clear the FIFO 
CHK_ERR	MOVEP	#%010000,X:PDRD		; Clear RS* low for 2 milliseconds
	MOVE	#200000,Y0
	DO	Y0,R_FIFO
	NOP
R_FIFO
	MOVEP	#%010100,X:PDRD		; Data Register - Set RS* high

; Check for the Read Image bit in the STATUS word. This is a way to avoid
;   putting the READ_IMAGE routine in an interrupt service routine. 
GET_RDI	JCLR	#RDI,X:<STATUS,GET_PCI	; If the bit is clear don't read image
	JMP	<READ_IMAGE		; Go read the image

; This routine processes PCI writes from the host, which are only writes to
;   update either the argument table ARG_TBL or the timing table TIM_TBL

GET_PCI	JCLR	#SRRQ,X:DSR,GET_FO	; First get the PCI address (IAE = 1)
	MOVEP	X:DRXR,A		; LSW of PCI address
	CMP	#$20,A			; PCI address must be >= $20
	JLT	<ERROR			; The low address is out of range
	CMP	#(TIM_TBL-ARG_TBL)*2+$20,A
	BGE	WR_TIM_TBL		; Write to the timing table
	LSR	A			; Byte -> 16-bit word address
	ADD	#(ARG_TBL-$10),A	; DSP addr = (PCI addr.-$20)/2 + ARG_TBL
	NOP				; Pipeline restriction
	MOVE	A1,R0
	JCLR	#SRRQ,X:DSR,*		; Wait for receiver to be not empty
	MOVEP	X:DRXR,A		; MSW of PCI address

; Get the data number and write it to the argument table
	JCLR	#SRRQ,X:DSR,*		; Wait for receiver to be not empty
	MOVEP	X:DRXR,X0		; Get least significant word
	JCLR	#SRRQ,X:DSR,*
	MOVEP	X:DRXR,X1		; Get most significant word
	MOVE	X1,X:(R0)+		; Store MSW in the argument table
	MOVE	X0,X:(R0)		; Store LSW in the argument table
	MOVE	R0,A
	CMP	#COMMAND_LSW,A		; Is it a command?
	JEQ	<MANUAL_COMMAND		; Yes - process the command
	JMP	<FINISH			; Write 'DON' reply

; Write the word to the timing board and to the PCI timing table TIM_TBL
WR_TIM_TBL
	MOVEP	X:DRXR,B			; MSW of PCI address
	CMP	#(TIM_TBL-ARG_TBL)*4+TIM_LEN,A	; Don't write beyond TIM_TBL
	JGT	<ERROR
	CMP	#(TIM_TBL-ARG_TBL)*2+$20,A 	; If exposure time write it
	JEQ	<TX_EXPT
	MOVE	A1,Y1
	MOVE	X:<C000204,A			; Timing board header
	JSR	<XMT_WRD			; Transmit header word
	MOVE	X:<CWRM,A
	JSR	<XMT_WRD			; Transmit  command = 'WRM'

	MOVE	Y1,A1					; Convert from PCI to 
	SUB	#((TIM_TBL-ARG_TBL)*2+$20+$08),A 	;   timing board address
	LSR	#2,A
	NOP				; Pipeline restriction
	BSET	#22,A1			; Y: memory on timing board
	JSR	<XMT_WRD		; Transmit encoded address
	MOVE	Y1,A1			; Restore PCI address
	LSR	#2,A
	SUB	#((TIM_TBL-ARG_TBL)/2+$08-TIM_TBL),A ; Timing table address
	JCLR	#SRRQ,X:DSR,*		; Wait for receiver to be not empty
	MOVEP	X:DRXR,X0		; Get least significant word = LSW
	JCLR	#SRRQ,X:DSR,*
	MOVEP	X:DRXR,X1		; Get most significant word = MSW
	MOVE	A1,R0			; A1 now has the address
	JSR	<SQUASH			; X1,X0 -> A1
	MOVE	A1,X:(R0)		; Write to the PCI timing table
	JSR	<XMT_WRD		; Transmit data
	JMP	<GET_FO			; Reply is generated by controller

; Special case - transmit the exposure time
	IF	@SCP("MASTER","TIMING")
TX_EXPT	MOVE	X:<HEADER_3,A
	JSR	<XMT_WRD		; Transmit header word
	MOVE	#'SET',A		; Set Exposure Time
	JSR	<XMT_WRD		; Transmit ASCII command
	ELSE
TX_EXPT	MOVE	X:<C000304,A
	JSR	<XMT_WRD		; Transmit header word
	MOVE	X:<CWRM,A
	JSR	<XMT_WRD		; Transmit ASCII command
	MOVE	#$400018,A
	JSR	<XMT_WRD		; Transmit exposure time address
	ENDIF
	JCLR	#SRRQ,X:DSR,*		; Wait for receiver to be not empty
	MOVEP	X:DRXR,X0		; Get least significant word = LSW
	JCLR	#SRRQ,X:DSR,*
	MOVEP	X:DRXR,X1		; Get most significant word = MSW
	JSR	<SQUASH
	JSR	<XMT_WRD		; Transmit exposure time data
	MOVE	A1,X:EXPTIME		; Write to the PCI timing table
	JMP	<GET_FO			; Reply is generated by controller

; ****************  Miscellaneous camera support commands  ***************

LOAD_APPLICATION
	MOVE	X:<COM_DEST,A		; Determine the command destination
	CMP	#2,A
	JNE	<LDA_UTL
	MOVE	X:<C000203,A
	JMP	<LDA
LDA_UTL	CMP	#3,A
	JNE	<ERROR_RTI
	MOVE	X:<C000303,A
LDA	JSR	<XMT_WRD		; Transmit header word
	MOVE	#'LDA',A
	JSR	<XMT_WRD		; Transmit ASCII command = 'LDA'
	MOVE	X:<ARG1_LSW,X0	
	MOVE	X:<ARG1_MSW,X1
	JSR	<SQUASH
	JSR	<XMT_WRD		; Transmit application number
	RTI				; Reply is generated by controller

READ_CONTROLLER_CONFIGURATION
	MOVE	X:<C000202,A
	JSR	<XMT_WRD		; Transmit timing board header word
	MOVE	#'RCC',A		; Read Controller Configuration
	JSR	<XMT_WRD		; Transmit ASCII command
	RTI				; Reply is generated by controller

READ_CONTROLLER_STATUS
	MOVE	X:<C000203,A
	JSR	<XMT_WRD		; Transmit timing board header word
	MOVE	X:<CRDM,A		; Command is read memory
	JSR	<XMT_WRD		; Transmit ASCII command
	MOVE	#$200000,A		; Address = X:0 = X:STATUS
	JSR	<XMT_WRD 
	RTI

WRITE_CONTROLLER_STATUS
	MOVE	X:<C000204,A
	JSR	<XMT_WRD		; Transmit timing board header word
	MOVE	X:<CWRM,A		; Command is write memory
	JSR	<XMT_WRD		; Transmit ASCII command
	MOVE	#$200000,A		; Address = X:0 = X:STATUS
	JSR	<XMT_WRD 
	MOVE	X:<ARG1_LSW,X0		; First argument
	MOVE	X:<ARG1_MSW,X1
	JSR	<SQUASH
	MOVE	A1,X:TIM_STAT		; Write to the PCI timing table
	JSR	<XMT_WRD

	IF	@SCP("MASTER","UTILITY")
	MOVE	X:<C000304,A
	JSR	<XMT_WRD		; Transmit timing board header word
	MOVE	X:<CWRM,A		; Command is write memory
	JSR	<XMT_WRD		; Transmit ASCII command
	MOVE	#$200001,A		; Location = X:1
	JSR	<XMT_WRD 
	JSET	#SHUTTER,X:ARG1_LSW,L_WCS0 ; Shutter control bit
	CLR	A
	JSR	<XMT_WRD		; Transmit 0 = don't open shutter
	JMP	<WCS_RTI
L_WCS0	MOVE	X:<ONE,A
	JSR	<XMT_WRD		; Transmit 1 = open shutter
	ENDIF
WCS_RTI	RTI

READ_PCI_STATUS
	MOVE	X:<STATUS,A
	JSR	<UNSQUASH
	JMP	<FINISH1_RTI

POWER_ON
	MOVE	X:<HEADER_2,A
	JSR	<XMT_WRD		; Transmit header word
	MOVE	#'PON',A
	JSR	<XMT_WRD		; Transmit ASCII command
	RTI				; Reply is generated by controller

POWER_OFF
	MOVE	X:<HEADER_2,A
	JSR	<XMT_WRD		; Transmit header word
	MOVE	#'POF',A
	JSR	<XMT_WRD		; Transmit ASCII command
	RTI				; Reply is generated by controller

SET_BIAS_VOLTAGES
	MOVE	X:<C000202,A
	JSR	<XMT_WRD		; Transmit header word
	MOVE	#'SBV',A
	JSR	<XMT_WRD		; Transmit ASCII command
	RTI				; Reply is generated by controller

CLEAR_ARRAY
	MOVE	X:<C000202,A
	JSR	<XMT_WRD		; Transmit header word
	MOVE	#'CLR',A
	JSR	<XMT_WRD		; Transmit ASCII command
	RTI				; Reply is generated by controller

STOP_IDLE_MODE
	MOVE	X:<C000202,A
	JSR	<XMT_WRD		; Transmit header word
	MOVE	#'STP',A
	JSR	<XMT_WRD		; Transmit ASCII command
	RTI				; Reply is generated by controller

RESUME_IDLE_MODE
	MOVE	X:<C000202,A
	JSR	<XMT_WRD		; Transmit header word
	MOVE	#'IDL',A
	JSR	<XMT_WRD		; Transmit ASCII command
	RTI				; Reply is generated by controller

ABORT_EXPOSURE
	MOVE	X:<HEADER_2,A
	JSR	<XMT_WRD		; Transmit header word
	MOVE	#'AEX',A
	JSR	<XMT_WRD		; Transmit ASCII command
	RTI				; Reply is generated by controller

PAUSE_EXPOSURE
	MOVE	X:<HEADER_2,A
	JSR	<XMT_WRD		; Transmit header word
	MOVE	#'PEX',A
	JSR	<XMT_WRD		; Transmit ASCII command
	RTI				; Reply is generated by controller

RESUME_EXPOSURE
	MOVE	X:<HEADER_2,A
	JSR	<XMT_WRD		; Transmit header word
	MOVE	#'REX',A
	JSR	<XMT_WRD		; Transmit ASCII command
	RTI				; Reply is generated by controller

OPEN_SHUTTER
	MOVE	X:<HEADER_2,A
	JSR	<XMT_WRD		; Transmit header word
	MOVE	#'OSH',A
	JSR	<XMT_WRD		; Transmit ASCII command
	RTI				; Reply is generated by controller

CLOSE_SHUTTER
	MOVE	X:<HEADER_2,A
	JSR	<XMT_WRD		; Transmit header word
	MOVE	#'CSH',A
	JSR	<XMT_WRD		; Transmit ASCII command
	RTI				; Reply is generated by controller

;SET_ARRAY_TEMPERATURE
;	MOVE	X:<C000303,A
;	JSR	<XMT_WRD		; Transmit header word
;	MOVE	#'SAT',A
;	JSR	<XMT_WRD		; Transmit ASCII command
;	MOVE	X:<ARG1_LSW,X0		; The argument is the Target temperature
;	MOVE	X:<ARG1_MSW,X1		;   temperature
;	JSR	<SQUASH
;	JSR	<XMT_WRD
;	RTI				; Reply is generated by controller

;READ_ARRAY_TEMPERATURE
;	MOVE	X:<C000302,A
;	JSR	<XMT_WRD		; Transmit header word
;	MOVE	#'RAT',A
;	JSR	<XMT_WRD		; Transmit ASCII command
;	RTI				; Reply is generated by controller

SET_ARRAY_TEMPERATURE
	MOVE	X:<C000304,A
	JSR	<XMT_WRD		; Transmit header word
	MOVE	X:<CWRM,A
	JSR	<XMT_WRD		; Transmit ASCII command
	MOVE	#$40001C,A
	JSR	<XMT_WRD		; Transmit target temperature address
	MOVE	X:<ARG1_LSW,X0		; First argument is the temperature
	MOVE	X:<ARG1_MSW,X1
	JSR	<SQUASH
	JSR	<XMT_WRD		; Transmit target temperature
	RTI				; Reply is generated by controller

READ_ARRAY_TEMPERATURE
	MOVE	X:<C000303,A
	JSR	<XMT_WRD		; Transmit header word
	MOVE	X:<CRDM,A
	JSR	<XMT_WRD		; Transmit ASCII command
	MOVE	#$40000C,A
	JSR	<XMT_WRD		; Transmit actual temperature address
	RTI				; Reply is generated by controller


; ****************  Exposure and camera control commands  ****************

; Read Exposure Time
READ_EXPOSURE_TIME
	IF	@SCP("MASTER","TIMING")
	MOVE	X:<C000202,A
	JSR	<XMT_WRD		; Transmit header word
	MOVE	#'RET',A
	JSR	<XMT_WRD		; Transmit ASCII command
	ELSE
	MOVE	X:<C000303,A
	JSR	<XMT_WRD		; Transmit header word
	MOVE	X:<CRDM,A
	JSR	<XMT_WRD		; Transmit ASCII command = 'RDM'
	MOVE	#$400017,A
	JSR	<XMT_WRD		; Transmit exposure time address
	ENDIF
	RTI				; Reply is generated by controller

; Send an abort readout command to the controller to stop image transmission
ABORT_READOUT
	BSET	#CLRT,X:DPCR		; Clear the transmitter
	JSET	#CLRT,X:DPCR,*		; Wait for the clearing to be complete	
	MOVE	X:<C000202,A
	JSR	<XMT_WRD		; Timing board header word
	MOVE	#'ABR',A
	JSR	<XMT_WRD		; Abort Readout

; Ensure that image data is no longer being received from the controller
ABR0	JCLR	#EF,X:PDRD,ABR2		; Test for incoming FIFO data
ABR1	MOVEP	Y:RDFIFO,X0		; Read the FIFO until its empty
	NOP
	JSET	#EF,X:PDRD,ABR1
ABR2	DO	#2400,ABR3		; Wait for about 30 microsec in case
	NOP				;   FIFO data is still arriving
ABR3	JSET	#EF,X:PDRD,ABR1		; Keep emptying if more data arrived
	BSET	#MODE,X:PDRD		; Put the fiber optics in 32-bit mode

; Clean up the PCI board from wherever it was executing
CLEAN_UP_PCI
	BCLR	#RDI,X:<STATUS		; Clear the read image bit
	MOVEP	#$0001C0,X:IPRC		; Disable HF* FIFO interrupt

	BSET	#DCTR_RPLY,X:DCTR	; Set reply interrupt bit
	BSET	#DCTR_BUF1,X:DCTR	; Set Buffer 1 interrupt bit
	BSET	#DCTR_BUF0,X:DCTR	; Set Buffer 0 interrupt bit

;	JCLR	#INTA,X:DCTR,L_WAIT	; If cleared, then assert without delay
;	JSET	#INTA,X:DCTR,*		; Wait for the interrupt to be cleared
;	REP	#800			; Wait about 10 microseconds
;	NOP
;L_WAIT	BSET	#INTA,X:DCTR		; Assert the interrupt

	MOVEC	#1,SP			; Point stack pointer to the top	
	MOVEC	#$000200,SSL		; SR = zero except for interrupts
	MOVEC	#0,SP			; Writing to SSH preincrements the SP
	MOVEC	#START,SSH		; Set PC to for full initialization
	NOP
	JMP	<FINISH_RTI		; Write 'DON' to the host computer

; Issue a read array command to the controller to get an image right away
READ_ARRAY
	MOVE	X:<C000202,A
	JSR	<XMT_WRD		; Transmit header word
	MOVE	#'RDC',A
	JSR	<XMT_WRD		; Transmit ASCII command
	RTI				; Reply is generated by controller

; Start a real exposure
START_EXPOSURE
	MOVE	X:<HEADER_2,A
	JSR	<XMT_WRD		; Header word
	MOVE	#'SEX',A
	JSR	<XMT_WRD		; Start Exposure

; Wait the for the header, and just discard it
	JCLR	#EF,X:PDRD,*		; Test for fiber optic data
	MOVEP	Y:RDFIFO,X0		; Read the first fiber optic word	
	REP	#16
	NOP
	MOVEP	Y:RDFIFO,X1		; Read the second fiber optic word
	NOP				; Wait for EF to settle

; Check for the exposure time reply
	JSR	<GET_REPLY		; Move the FIFO reply into A1
	CMP	#'DON',A
	JNE	<ERROR_RTI		; There was an error

; If the exposure time is 5000 milliseconds or less then jump right to
;   READ_IMAGE so host computer latencies will not mess up the image taking
	MOVE	X:EXPTIME,A		; Get the desired image exposure time
	CMP	#5000,A			; Jump to FINISH_RTI if EXPTIME > 5000
	JGT	*+2
	BSET	#RDI,X:<STATUS		; Set the Read Image bit
	JMP	<FINISH_RTI		; Write 'DON' to the host computer


; *************************************************************************
;  There are several address register assignements in the Scatter/Gather 
;    routine that should not be disturbed
;
;	R1 - DRAM address of pixel being scaterred
;	R2 - address in X_TABLE of block being scatterred
;	R4 - address in X_TABLE of block being gathered
;	R5 - DRAM address of pixel being gathered
;	R0, R3, R6 and R7 are not used in the Scatter/Gather routine
;
; *************************************************************************

; Read the image - change the serial receiver to expect 16-bit (image) data
READ_IMAGE
	BCLR	#MODE,X:PDRD		; Put the fiber optics in 16-bit mode

; Set up for scattering
	BSET	#SCATTERING,X:<STATUS	; We've begun scattering the image
	MOVE	X:<ONE,A
	NOP
	MOVE	A,X:<IBLK_SCATTER
	MOVE	A,X:<IBLK_GATHER
	CLR	A
	MOVE	#X_TABLE,R4		; Zero out the SG table
	DO	#N_TABLE,ZERO_TABLE
	MOVE	A,X:(R4)+
ZERO_TABLE
	JSR	<INIT_SCATTER_BLOCK

; Enable HF* interrupts
	MOVEP	#$0001D0,X:IPRC		; Enable FIFO HF* interrupt
	MOVE	#$100,SR		; Enable level one interrupts

; Compute parameters for the scatter/gather algorithmn
	MOVE	X:NCOLS,X0
	MOVE	X:NROWS,Y0
	MPY	X0,Y0,A			; A = number of bytes in image
	ASR	#1,A,B			; Now its a pixel counter in Acc B
	NOP				; Pipeline restriction
	MOVE	B0,X:<IPXLS_SCATTER_0	; Number of pixels to scatter
	MOVE	B1,X:<IPXLS_SCATTER_1
	MOVE	B0,X:<IPXLS_GATHER_0	; Number of pixels to gather
	MOVE	B1,X:<IPXLS_GATHER_1

; Do miscellaneous preparations
	BCLR	#ODD_EVEN,X:<STATUS	; Initialize to even buffer numbers
	BSET	#CLRT,X:DPCR		; Clear the transmitter
	JSET	#CLRT,X:DPCR,*		; Wait for the clearing to be complete
	MOVEP	X:DPSR,A		; Clear all PCI error conditions
	OR	#$1FE,A
	NOP
	MOVEP	A,X:DPSR
	MOVE	X:<FOUR,Y0		; For adding to B0, not B1 !?!
	MOVE	#0,Y1			; !!!

; Set up for gathering
	BSET	#GATHERING,X:<STATUS	; We've begun gathering the image too
GATHER7	MOVE	X:<BLOCK_SIZE,X0
	MOVE	X0,X:<NUM_GATHER
	MOVE	#0,X1
	CLR	A
	MOVE	X:<IPXLS_GATHER_0,A0	; Number of pixels to gather
	MOVE	X:<IPXLS_GATHER_1,A1
	SUB	X,A			; 56-bit subtraction
	JGT	<SETUP
	ADD	X,A
	BCLR	#GATHERING,X:<STATUS	; This is the last gathering block
	MOVE	A0,X:<NUM_GATHER	; Do loop index = BLOCK_SIZE
					;   except on the last block

; Choose the odd or even PCI buffer and check that it can be written to
SETUP	CLR	B
	MOVE	A0,X:<IPXLS_GATHER_0	; Save number of pixels left to gather
	MOVE	A1,X:<IPXLS_GATHER_1
	BTST	#ODD_EVEN,X:<STATUS	; Check for odd or even PCI buffer
	JCC	<EVEN			

; Write to the odd block numbers from here, through buffer #1
	MOVE	X:ADR_BLOCK_1_B0,B0	; Acc B will contain the PCI address
	MOVE	X:ADR_BLOCK_1_B1,X0	; Convert two 16-bit address chunks
	INSERT	#$010010,X0,B		;   into one 32-bit address
TSTBUF1
	JCLR	#DCTR_BUF1,X:DCTR,TSTDSR1	; Check for host interrupt
	JMP	<TSTBUF1	
TSTDSR1	JCLR	#DSR_BUF1,X:DSR,GATHER		; Check host user buffer writing
	JMP	<TSTBUF1

; Write to the even block numbers from here, through buffer #0
EVEN	MOVE	X:ADR_BLOCK_0_B0,B0
	MOVE	X:ADR_BLOCK_0_B1,X0
	INSERT	#$010010,X0,B
TSTBUF0
	JCLR	#DCTR_BUF0,X:DCTR,TSTDSR0	; Check host interrupt
	JMP	<TSTBUF0
TSTDSR0	JCLR	#DSR_BUF0,X:DSR,GATHER		; Check host user buffer writing
	JMP	<TSTBUF0

; Set up to GATHER from DRAM to PCI. Find the next block number 
GATHER	MOVE	#X_TABLE,R4		; R4 = TABLE index
	DO	#N_TABLE,GATHER0	; Search through TABLE for a block
	MOVE	X:(R4),A		;  that needs to be GATHERed to PCI
	JSET	#BUSY,X:(R4),GATHER1	; Skip over block if its busy	
	TST	A 
	JEQ	<GATHER1
	LSR	#2,A
	MOVE	X:<IBLK_GATHER,X0	; Search for the correct block number
	CMP	X0,A
	JNE	<GATHER1
	ENDDO
	JMP	<GATHER6
GATHER1 MOVE	(R4)+
GATHER0
	JCLR	#RDI,X:<STATUS,GET_PCI	; Exit if not reading out
	JMP	<GATHER

GATHER6
	MOVE	R4,A			; The table address encodes the
	NOP				;   DRAM address
	SUB	#(X_TABLE-1),A
	LSL	#16,A
	MOVE	X:<ONE,X0
	MOVE	A1,R5			; DRAM memory address for PCI writes
	MOVE	X0,X:(R4)		; Number of block = 0, BUSY = 1

; Fill the Transmit FIFO so we can tell if the pixel data has been written
;   to the PCI bus by testing for the transmit FIFO being not full (MTRQ bit)
	BSET	#CLRT,X:DPCR		; Clear the transmitter
	JSET	#CLRT,X:DPCR,*		; Wait for the clearing to be complete
	DO	#8,GATHER9
	MOVEP	Y:(R5)+,X:DTXM		; Write pixel data to transmit FIFO
GATHER9
	MOVE	X:<NUM_GATHER,A
	NOP
	LSR	#1,A			; Number of PCI writes per block
	NOP

; Write the image block to the PCI bus
	DO	A1,GATHER3
	EXTRACTU #$010010,B,A		; Get D31-16 bits only
	NOP
	MOVEP	A0,X:DPMC		; DSP master control register
	NOP
	EXTRACTU #$010000,B,A
	NOP
	MOVE	A0,A1
	OR	#$070000,A		; A1 gets written to DPAR register
	NOP
GATHER8	MOVEP	A1,X:DPAR		; Write to PCI bus
	NOP				; Pipeline delay

WT_XTM	JSET	#MTRQ,X:DPSR,GATHER4	; If MTRQ = 1 go for the next two pixels
	JCLR	#TRTY,X:DPSR,WT_XTM	; Bit is set if its a retry
	MOVEP	#$0400,X:DPSR		; Clear bit 10 = target retry bit
	JCLR	#MARQ,X:DPSR,*		; Wait for PCI addressing to be complete
	JMP	<GATHER8

GATHER4	MOVEP	Y:(R5)+,X:DTXM		; Least significant word to transmit
	MOVEP	Y:(R5)+,X:DTXM		; Most significant word to transmit
GATHER5	ADD	Y,B			; Increment PCI address
	NOP
GATHER3

	MOVE	X:<IBLK_GATHER,A	; Increment gathered block number
	ADD	#1,A
	NOP
	MOVE	A1,X:<IBLK_GATHER
	BCLR	#BUSY,X:(R4)		; Clear busy bit of Gather SGT entry

	BCHG	#ODD_EVEN,X:<STATUS	; Check for odd or even PCI buffer
	JCC	<EVEN_BLK
	BSET	#DCTR_BUF1,X:DCTR	; Buffer 1 is interrupting
	JMP	<GATHER2
EVEN_BLK BSET	#DCTR_BUF0,X:DCTR	; Buffer 0 is interrupting

GATHER2	BSET	#INTA,X:DCTR		; Assert PCI interrupt
	JSET	#GATHERING,X:<STATUS,GATHER7	; See if we're on the last block

	BSET	#MODE,X:PDRD		; Put the fiber optics in 32-bit mode
	MOVEP	#$0001C0,X:IPRC		; Disable FIFO HF* interrupts
	MOVE	#$200,SR
	BCLR	#RDI,X:<STATUS		; Clear the read image bit
	JMP	<FINISH			; Write 'DON' to the host computer

; Set up the SCATTER process for the next block - read from FIFO and  
;   write to random DRAM blocks
INIT_SCATTER_BLOCK
	MOVE	#X_TABLE,R2		; R2 = TABLE index
	DO	#N_TABLE,SCATTER0	; Search through TABLE for a slot
	MOVE	X:(R2),A		; Get SGT entry
	JSET	#BUSY,X:(R2),SCATTER1	; Skip over it if its busy	
	TST	A
	JNE	<SCATTER1		; Skip over if block number is non-zero
	MOVE	R2,A
	SUB	#(X_TABLE-1),A		; Correct for X_TABLE address
	LSL	#16,A
	NOP
	MOVE	A1,R1			; DSP memory address
	MOVE	X:<IBLK_SCATTER,A	; Get the current SCATTER block number
	LSL	#2,A			; Convert it to a S/G table entry
	NOP
	BSET	#BUSY,A1		; Set the BUSY bit and write it to
	NOP				;   the S/G table
	MOVE	A1,X:(R2)
	MOVE	#>NRDFIFO,X0		; Number of 512 pixel FIFO chunks 
	MOVE	X0,X:<IRDFIFO		;   per image block
	ENDDO
	JMP	<SCATTER0
SCATTER1 MOVE	(R2)+			; Increment to next SGT entry
SCATTER0
	MOVE	X:<IBLK_SCATTER,A	; Increment to number of next 
	ADD	#1,A			;   scatter block
	NOP
	MOVE	A1,X:<IBLK_SCATTER
	RTS

; Scatter half the FIFO to DRAM. First save registers to be used here
SCATTER_FIFO
	MOVEP	#$0001C0,X:IPRC		; Disable FIFO HF* interrupt
	MOVE	A0,X:<SV_A0		; Save registers used here
	MOVE	A1,X:<SV_A1
	MOVE	X0,X:<SV_X0
	MOVE	X1,X:<SV_X1

	JCLR	#SCATTERING,X:STATUS,RTIFIFO	 ; Are we still scattering?

; Compute number of pixels to read from FIFO, 512 maximum
	MOVE	X:<C512,X0		; 1/2 the FIFO depth
	MOVE	#0,X1
	MOVE	X:<IPXLS_SCATTER_0,A0	; Number of pixels to scatter
	MOVE	X:<IPXLS_SCATTER_1,A1
	SUB	X,A
	NOP
	MOVE	A0,X:<IPXLS_SCATTER_0	; New number of pixels to scatter
	MOVE	A1,X:<IPXLS_SCATTER_1
	SUB	X,A
	JLE	<SCATTER7
	DO	X0,SCATTER3
	MOVEP	Y:RDFIFO,Y:(R1)+	; FIFO -> DRAM
SCATTER3
	MOVE	X:<IRDFIFO,A
	SUB	#1,A
	NOP
	MOVE	A1,X:<IRDFIFO
	JNE	<RTIFIFO
	BCLR	#BUSY,X:(R2)		; We are done with scattering this
	JSR	<INIT_SCATTER_BLOCK	;  block
	JMP	<RTIFIFO

; Scatter the last little chunk of the image if Npixels <= 512
SCATTER7 ADD	X,A
	ADD	X,A
	NOP
	DO	A0,SCATTER8
	JCLR	#EF,X:PDRD,*		; Wait for a pixel 
	NOP
	MOVEP	Y:RDFIFO,Y:(R1)+	; FIFO -> DRAM
SCATTER8
	BCLR	#BUSY,X:(R2)		; We're done scattering this block
	BCLR	#SCATTERING,X:<STATUS	; We are all done scattering

; Restore the registers that were used in this interrupt service routine
RTIFIFO
	MOVEP	#$0001D0,X:IPRC		; Re-enable FIFO HF* interrupt
	MOVE	X:<SV_A0,A0
	MOVE	X:<SV_A1,A1
	MOVE	X:<SV_X0,X0
	MOVE	X:<SV_X1,X1
	RTI

; ***** Test Data Link, Read Memory, Write Memory, and Manual Commands ******

; Test the data link by echoing back ARG1 from either PCI, TIM or UTL board
TEST_DATA_LINK
	MOVE	X:<COM_DEST,A		; Determine the command destination
	CMP	#1,A
	JNE	<TIM_TDL
PCI_TDL	MOVE	X:<ARG1_LSW,X0
	MOVE	X:<ARG1_MSW,X1
	JMP	<FINISH1_RTI
TIM_TDL	CMP	#2,A
	JNE	<UTL_TDL
	MOVE	X:<C000203,A
	JSR	<XMT_WRD
	JMP	<TDL_COM
UTL_TDL	CMP	#3,A
	JNE	<ERROR_RTI		; Not 1, 2 or 3 => error
	MOVE	X:<C000303,A
	JSR	<XMT_WRD
TDL_COM	MOVE	#'TDL',A
	JSR	<XMT_WRD
	MOVE	X:<ARG1_LSW,X0
	MOVE	X:<ARG1_MSW,X1
	JSR	<SQUASH
	JSR	<XMT_WRD
	RTI				; Reply is generated by controller	

; Read from memory, either PCI, timing or utility board
READ_MEMORY
	MOVE	X:<COM_DEST,A	; Determine the command destination
	CMP	#1,A
	JNE	<TIM_RDM
	MOVE    X:<ARG2_LSW,X0	; Get the address
	MOVE    X:<ARG2_MSW,X1
	JSR	<SQUASH		; Squash it from X1,X0 into A1
	MOVE	A1,R0
	MOVE	X:<ARG1_LSW,A	; Memory type (X, Y, P, R or D)
	CMP	#$005F50,A	; $00'_P'
	JNE	<RDX
	MOVE	P:(R0),A1	; Read from Program Memory
	JSR	<UNSQUASH	; A1 -> X1,X0
        JMP     <FINISH1_RTI	; Send out a header with the value
RDX
	CMP	#$005F58,A	; $00'_X'
	JNE	<RDY
        MOVE    X:(R0),A1	; Read from X data memory
	JSR	<UNSQUASH
        JMP     <FINISH1_RTI	; Send out a header with the value
RDY
	CMP	#$005F59,A	; $00'_Y'
	JNE	<RDR
        MOVE    Y:(R0),A1	; Read from Y data memory
	JSR	<UNSQUASH
	JMP     <FINISH1_RTI	; Send out a header with the value
RDR
	CMP	#$005F52,A	; $00'_R'
	JNE	<ERROR
	BSET	#1,X:PDRC	; ROM/FIFO* = 1 to select ROM
	MOVEP	#$008C29,X:AAR1	; P: = $008000 to $008777 asserts AA1 low true
	MOVEP	#$0002A0,X:BCR	; Bus Control Register for slow EEPROM
	MOVE	X:<THREE,X0	; Convert to word address to a byte address
	MOVE	R0,Y0		; Get 16-bit address in a data register
	MPY	X0,Y0,A		; Multiply	
	ASR	A		; Eliminate zero fill of fractional multiply
	MOVE	A0,R0		; Need to address memory
	BSET	#15,R0		; Set bit so its in EEPROM space
	DO      #3,L1RDR
	MOVE    P:(R0)+,A2      ; Read each ROM byte
	ASR     #8,A,A		; Move right into A1
	NOP
L1RDR
	JSR	<UNSQUASH
	BCLR	#1,X:PDRC	; ROM/FIFO* = 0 to select FIFO
	MOVEP	#$FFFC21,X:AAR1	; Restore FIFO addressing
	MOVEP	#$000020,X:BCR	; Restore fast FIFO access
	JMP     <FINISH1_RTI

; Its a read from either the timing or the utility board memory
TIM_RDM	CMP	#2,A
	JNE	<UTL_RDM
	MOVE	X:<C000203,A		; Transmit header to timing board
	JSR	<XMT_WRD
	JMP	<RDM_COM
UTL_RDM	CMP	#3,A
	JNE	<ERROR_RTI		; Not 1, 2 or 3 => error
	MOVE	X:<C000303,A		; Transmit header to utility board
	JSR	<XMT_WRD
RDM_COM	MOVE	X:<CRDM,A		; Command = RDM
	JSR	<XMT_WRD
	JSR	<ENC_ADR		; Encoded address
	JSR	<XMT_WRD
	RTI				; Reply is generated by controller	

; Program WRMEM - write to PCI memory, reply 'DON'
WRITE_MEMORY
	MOVE	X:<COM_DEST,A	; Determine the command destination
	CMP	#1,A
	JNE	<TIM_WRM
	MOVE    X:<ARG2_LSW,X0	; Get the address
	MOVE    X:<ARG2_MSW,X1
	JSR	<SQUASH		; Squash it from X1,X0 into A1
	MOVE	A1,R0
	MOVE    X:<ARG3_LSW,X0	; Get the data to be written
	MOVE    X:<ARG3_MSW,X1
	JSR	<SQUASH		; Squash it from X1,X0 into A1
	MOVE	A1,X0		; X0 = data value
	MOVE	X:<ARG1_LSW,A	; Memory type (X, Y, P, R or D)
	CMP	#$005F50,A	; $00'_P'
        JNE	<WRX
        MOVE	X0,P:(R0)	; Write to Program memory
        JMP     <FINISH_RTI
WRX
	CMP	#$005F58,A	; $00'_X'
        JNE	<WRY
        MOVE    X0,X:(R0)	; Write to X: memory
        JMP     <FINISH_RTI
WRY
	CMP	#$005F59,A	; $00'_Y'
        JNE	<WRR	
        MOVE    X0,Y:(R0)	; Write to Y: memory
	JMP	<FINISH_RTI
WRR
	CMP	#$005F52,A	; $00'_R'
        JNE	<WR_ERR		; Test for EEPROM memory
	BSET	#1,X:PDRC	; ROM/FIFO* = 1 to select ROM
	MOVEP	#$008C29,X:AAR1	; P: = $008000 to $008777 asserts AA1 low true
	MOVEP	#$0002A0,X:BCR	; Bus Control Register for slow EEPROM
	MOVE	X:<THREE,X1	; Convert to word address to a byte address
	MOVE	R0,Y0		; Get 16-bit address in a data register
	MPY	X1,Y0,A		; Multiply	
	ASR	A		; Eliminate zero fill of fractional multiply
	MOVE	A0,R0		; Need to address memory
	BSET	#15,R0		; Set bit so its in EEPROM space
	MOVE    X0,A1           ; Get data from command string
	DO      #3,L1WRR	; Loop over three bytes of the word
	MOVE    A1,P:(R0)+      ; Write each EEPROM byte
	ASR     #8,A,A 		; Move right one byte
	MOVE	#400000,Y0
	DO      Y0,L2WRR	; Delay by 5 millisec for EEPROM write
	NOP
L2WRR
	NOP                     ; DO loop nesting restriction
L1WRR
	BCLR	#1,X:PDRC	; ROM/FIFO* = 0 to select FIFO
	MOVEP	#$FFFC21,X:AAR1	; Restore FIFO addressing
	MOVEP	#$000020,X:BCR	; Restore fast FIFO access
	JMP     <FINISH_RTI

WR_ERR	MOVE	#'ERR',X0	; Error return
	JMP	<FINISH_RTI
	
; Its a read from either the timing or the utility board memory
TIM_WRM	CMP	#2,A
	JNE	<UTL_WRM
	MOVE	X:<C000204,A		; Transmit header to timing board
	JSR	<XMT_WRD
	JMP	<WRM_COM
UTL_WRM	CMP	#3,A
	JNE	<ERROR_RTI		; Not 1, 2 or 3 => error
	MOVE	X:<C000304,A		; Transmit header to utility board
	JSR	<XMT_WRD
WRM_COM	MOVE	X:<CWRM,A		; Command = WRM
	JSR	<XMT_WRD
	JSR	<ENC_ADR		; Encoded address
	JSR	<XMT_WRD
	MOVE	X:<ARG3_LSW,X0		; Data to be written
	MOVE	X:<ARG3_MSW,X1
	JSR	<SQUASH
	JSR	<XMT_WRD
	RTI				; Reply is generated by controller

; Process a manual timing or utility board command
MANUAL_COMMAND
	MOVE	X:<COM_DEST,A		; Determine the command destination
	CMP	#1,A
	JEQ	<PCI_MAN		; Its a manual PCI command
	CMP	#2,A
	JEQ	<TIM_MAN
	JMP	<UTL_MAN

; Process a manual command to the PCI board
PCI_MAN	MOVE	X:<COMMAND_LSW,X0	; Get the command
	MOVE	X:<COMMAND_MSW,X1
	JSR	<SQUASH
	CMP	#'TRM',A		; Its the test DRAM command
	JEQ	<TEST_DRAM
	JMP	<ERROR			; Its not a recognized command

; Process a manual command to the timing board
TIM_MAN	MOVE	X:<NUM_ARG,A1
	ADD	#2,A
	MOVE	X:<C000200,X0
	ADD	X0,A
	JSR	<XMT_WRD		; Transmit header word to timing board
	JMP	<WRM_MAN

; Process a manual command to the utility board
UTL_MAN	CMP	#3,A
	JNE	<ERROR			; Not 1, 2 or 3 => error
	MOVE	X:<NUM_ARG,A
	ADD	#2,A
	MOVE	X:<C000300,X0
	ADD	X0,A
	JSR	<XMT_WRD		; Transmit header word to utility board
WRM_MAN	MOVE	X:<COMMAND_LSW,X0
	MOVE	X:<COMMAND_MSW,X1
	JSR	<SQUASH
	JSR	<XMT_WRD		; Transmit command word
	MOVE	X:<NUM_ARG,A
	TST	A
	JEQ	<GET_FO			; If number of arguments = 0 return
	MOVE	#ARG1_MSW,R0
	DO	X:<NUM_ARG,L_MANUAL
	MOVE	X:(R0)+,X1		; MSW of argument
	MOVE	X:(R0)+,X0		; LSW of argument

	JSR	<SQUASH			; X1,X0 -> A1
	JSR	<XMT_WRD		; Transmit arguments
	NOP
L_MANUAL
	JMP	<GET_FO	

;  ***************  Subroutines used all over the place  ******************
;
; Routine for returning from the interrupt on an error
ERROR_RTI
	MOVE	#'RR',X0		; Report an error
	MOVE	#>'E',X1
	JSR	<EXECUTE_FINISH
	RTI				; Return from long interrupt

; Routine for returning from the interrupt with a 'DON' successful message
FINISH_RTI
	MOVE	#'ON',X0		; Report DON
	MOVE	#>'D',X1
	JSR	<EXECUTE_FINISH
	RTI				; Return from long interrupt

; Routine for returning from the interrupt with a 'DON' successful message
FINISH1_RTI
	JSR	<EXECUTE_FINISH
	RTI				; Return from long interrupt

; Start of miscellaneous support routines
ERROR	MOVE	#'RR',X0		; Report an error
	MOVE	#>'E',X1
	JMP	<FINISH1
FINISH	MOVE	#'ON',X0		; Report DON
	MOVE	#>'D',X1
FINISH1	JSR	<EXECUTE_FINISH
	JMP	<GET_PCI

; Write the reply to the slave transmit FIFO
EXECUTE_FINISH
	CLR	A
	MOVE	#100000,A0		; Wait a maximum of about 5 millisec
					;   for the transmitter to be NOT full
L_XMT0	TST	A
	JGT	<L_XMT1
	BSET	#CLRT,X:DPCR		; Clear the transmitter
	JSET	#CLRT,X:DPCR,*		; Wait for the clearing to be complete
	JMP	<L_XMT2
L_XMT1	JSET	#STRQ,X:DSR,L_XMT2	; Make sure the transmitter is not full
	DEC	A
	JMP	<L_XMT0
L_XMT2	
	MOVEP	X0,X:DTXS		; DSP-to-host slave transmit
	NOP
	MOVEP	X1,X:DTXS		; DSP-to-host slave transmit
	NOP

; Assert the interrupt if its not already asserted
	CLR	A
	JCLR	#INTA,X:DCTR,L_XMT8	; If cleared, then assert without delay
	MOVE	#1000000,A0		; Wait about 50 milliseconds for the
L_XMT5	TST	A			;   interrupt to be clear
	JGT	<L_XMT6
	RTS				;   If it isn't then just return
L_XMT6	JCLR	#INTA,X:DCTR,L_XMT7	; If clear, then jump out
	DEC	A
	JMP	<L_XMT5
L_XMT7	DO	#800,*+3		; Wait about 10 microseconds
	NOP
L_XMT8	BSET	#INTA,X:DCTR		; Assert the interrupt
	BSET	#DCTR_RPLY,X:DCTR	; Set reply interrupt flag
	RTS

; Convert 2 x 16-bit PCI words in X0 and X1 into one 24-bit DSP word in A1
SQUASH	MOVE	X1,A
	LSL	#16,A
	ADD	X0,A
	RTS

; Convert one 24-bit DSP word in A into 2 x 16-bit PCI words in X0 and X1
UNSQUASH				; Acc A1 --> X0 and X1
	MOVE	A1,B
	AND	#$00FFFF,B
	MOVE	B1,X0			; Least significant word - X0
	MOVE	A1,B
	LSR	#16,B
	NOP
	MOVE	B1,X1			; Most significant word = X1
	RTS

; Subroutine to encode memory type in the address
ENC_ADR	MOVE	X:<ARG1_LSW,B	; Memory type (X, Y, P, or R)
	MOVE    X:<ARG2_LSW,X0	; Get the address
	MOVE    X:<ARG2_MSW,X1
	JSR	<SQUASH		; Squash it from X1,X0 into A1
	CMP	#$005F50,B	; $00'_P'
	JNE	<NOT_P
	BSET	#20,A
	RTS
NOT_P
	CMP	#$005F58,B	; $00'_X'
	JNE	<NOT_X
	BSET	#21,A
	RTS
NOT_X
	CMP	#$005F59,B	; $00'_Y'
	JNE	<NOT_Y
	BSET	#22,A
	RTS
NOT_Y
	CMP	#$005F52,B	; $00'_R'
	JNE	<ERROR
	BSET	#23,A
	RTS

; Reset the controller by sending a special code for the preamble byte
RESET_CONTROLLER
	MOVEP	#%010100,X:PDRD		; Stop resetting the FIFO
	JCLR	#TDE,X:SSISR0,*
	MOVEP	#$000000,X:TX00
	NOP
	JCLR	#TDE,X:SSISR0,*		; Start bit
	MOVEP	#$010000,X:TX00
	NOP
	JCLR	#TDE,X:SSISR0,*
	MOVEP	#$530000,X:TX00		; Preamble byte -> reset
	NOP
	DO	#3,L_RESET
	JCLR	#TDE,X:SSISR0,*		; Three data bytes = anything	
	MOVEP	A1,X:TX00
	NOP
L_RESET
	JCLR	#TDE,X:SSISR0,*		; Zeroes to bring TX00 low
	MOVEP	#$000000,X:TX00

; Now wait around for the 'SYR' reply from system reset and the 'DON'
;   reply from the Load Application command
	JSR	<GET_REPLY		; Move the FIFO reply into A1
	CMP	#$020002,A
	JNE	<ERROR_RTI		; There was an error
	JSR	<GET_REPLY		; Move the FIFO reply into A1
	CMP	#'SYR',A
	JNE	<ERROR_RTI		; There was an error
	JSR	<GET_REPLY		; Move the FIFO reply into A1
	CMP	#$020002,A
	JNE	<ERROR_RTI		; There was an error
	JSR	<GET_REPLY		; Move the FIFO reply into A1
	CMP	#'DON',A
	JNE	<ERROR_RTI		; There was an error

; Reply to PCI bus and return from interrupt
	MOVE	#'YR',X0		; Report an system reset successful
	MOVE	#>'S',X1
	JSR	<EXECUTE_FINISH
	RTI				; Return from long interrupt

; Transmit contents of Accumulator A1 to the timing board
XMT_WRD	MOVE	A,X:SV_A
	JCLR	#TDE,X:SSISR0,*
	MOVEP	#$000000,X:TX00
	JSR	<XMT_DLY
	JCLR	#TDE,X:SSISR0,*		; Start bit
	MOVEP	#$010000,X:TX00
	JSR	<XMT_DLY
	JCLR	#TDE,X:SSISR0,*
	MOVEP	#$AC0000,X:TX00		; Preamble byte
	JSR	<XMT_DLY
	DO	#3,L_XMIT
	JCLR	#TDE,X:SSISR0,*		; Three data bytes	
	MOVEP	A1,X:TX00
	JSR	<XMT_DLY
	LSL	#8,A
L_XMIT
	JCLR	#TDE,X:SSISR0,*		; Zeroes to bring TX00 low
	MOVEP	#$000000,X:TX00
	JSR	<XMT_DLY
	MOVE	X:SV_A,A
	RTS

; Short delay for reliability
XMT_DLY	NOP
	NOP
	NOP
	RTS

; Read the reply from the fiber optics FIFO, check it and put it in A1
GET_REPLY
	JCLR	#EF,X:PDRD,*		; Wait for the third word 
	MOVEP	Y:RDFIFO,X0		; Read the FIFO word
	MOVE	X:<C00FF00,B		; DMASK = $00FF00
	AND	X0,B 
	CMP	#$00AC00,B  
	JEQ	<GT_RPLY		; If byte equalS $AC then continue
	MOVEP	#%010000,X:PDRD		; Clear RS* low for 2 milliseconds
	MOVE	#200000,Y0
	DO	Y0,*+3
	NOP
	MOVEP	#%010100,X:PDRD		; Data Register - Set RS* high
	MOVE	#'ERR',A		; Return error value
	RTS
GT_RPLY	MOVE	X0,B
	LSL	#16,B			; Shift byte in D7-D0 to D23-D16
	REP	#10
	NOP
	MOVE	Y:RDFIFO,X1		; Read the FIFO word
	MOVE	#$00FFFF,A
	AND	X1,A			; Select out D15-D0
	MOVE	B1,X1
	OR	X1,A			; Add D23-D16 to D15-D0
	RTS

; *******************  Miscellaneous testing routines  ******************
; Test Y: memory mapped to AA0 and AA2 from $000000 to $FFFFFF (16 megapixels)
; DRAM definitions 

TEST_DRAM

; Test Y: memory mapped to AA0 and AA2 from $000000 to $FFFFFF (16 megapixels)
	CLR	A
	NOP
	MOVE	A,R0
	MOVE	#$FF0000,Y0		; Y:$000000 to Y:$FEFFFF
	DO	Y0,L_WRITE_RAM0	
	MOVE	A1,Y:(R0)+
	ADD	#1,A
	NOP
L_WRITE_RAM0

	CLR	A
	NOP
	MOVE	A,R0
	MOVE	#$FF0000,Y0
	DO	Y0,L_CHECK_RAM0
	MOVE	Y:(R0)+,X0
	CMPU	X0,A
	JEQ	<L_RAM4
	ENDDO
	JMP	<ERROR_Y
L_RAM4	ADD	#1,A
	NOP
L_CHECK_RAM0

; Test X: memory mapped to AA3 from $1000 to $7FFFFF (8 megapixels)
	CLR	A
	MOVE	#$1000,R0			; Skip over internal X: memory
	MOVE	#$7FF000,Y0			; X:$001000 to X:$7FFFFF
	DO	Y0,L_WRITE_RAM3	
	MOVE	A,X:(R0)+
	ADD	#1,A
	NOP
L_WRITE_RAM3

	CLR	A
	MOVE	#$1000,R0
	MOVE	#$7FF000,Y0
	DO	Y0,L_CHECK_RAM3	
	MOVE	X:(R0)+,X0
	CMPU	X0,A
	JEQ	<L_RAM5
	ENDDO
	JMP	<ERROR_X
L_RAM5	ADD	#1,A
	NOP
L_CHECK_RAM3
	JMP	<FINISH

ERROR_Y	MOVE	#'__Y',X0
	MOVE	X0,X:<TRM_MEM
	MOVE	R0,X:<TRM_ADR	
	JMP	<ERROR
ERROR_X	MOVE	#'__X',X0
	MOVE	X0,X:<TRM_MEM
	MOVE	R0,X:<TRM_ADR	
	JMP	<ERROR

; For testing the ROM/FIFO* bit by toggling it indefinitely
SQ_WAVE	BSET	#ROM_FIFO,X:PDRC
	REP	#50
	NOP
	BCLR	#ROM_FIFO,X:PDRC
	REP	#50
	NOP
	JMP	<SQ_WAVE

;  ****************  Setup memory tables in X: space ********************

; Define the address in P: space where the table of constants begins

        ORG     X:VAR_TBL,P:

; Parameters
STATUS		DC	0		; Various status bis
REPLY		DC	0		; Is it OK to reply?

	IF	@SCP("DOWNLOAD","HOST")	; Download via host computer
CONSTANTS_TBL_START	EQU	@LCV(L)-2
	ENDIF

	IF	@SCP("DOWNLOAD","ROM")	; Boot ROM code
CONSTANTS_TBL_START	EQU	@LCV(L)-2
	ENDIF

	IF	@SCP("DOWNLOAD","ONCE")	; Download via ONCE debugger
CONSTANTS_TBL_START	EQU	@LCV(L)
	ENDIF

; Parameter table in P: space to be copied into X: space during 
;   initialization, and must be copied from ROM in the boot process
ONE		DC	1		; One
THREE		DC	3		; Three
FOUR		DC	4		; Four
EIGHT		DC	8		; Eight
C512		DC	512		; 1/2 the FIFO size
BLOCK_SIZE 	DC	$10000		; Scatter/gather block size = 64k pixels
C00FF00		DC	$00FF00
C0000F8		DC	$0000F8
C000200		DC	$000200		; Timing board header
C000300		DC	$000300		; Utility board header
C000202		DC	$000202		; Timing board header
C000302		DC	$000302		; Utility board header
C000203		DC	$000203		; Timing board header
C000303		DC	$000303		; Utility board header
C000204		DC	$000204		; Timing board header
C000304		DC	$000304		; Utility board header
CWRM		DC	'WRM'		; Write memory command
CRDM		DC	'RDM'		; Read Memory command
TRM_MEM		DC	0		; Test DRAM, memory type of failure
TRM_ADR		DC	0		; Test DRAM, address of failure

	IF	@SCP("MASTER","TIMING")
HEADER_2	DC	$000202		; Timing board header
HEADER_3	DC	$000203		; Timing board header
	ENDIF

	IF	@SCP("MASTER","UTILITY")
HEADER_2	DC	$000302		; Utility board header
HEADER_3	DC	$000303		; Utility board header
	ENDIF

; Tack the length of the variable table onto the length of code to be booted
CONSTANTS_TBL_LENGTH EQU	@CVS(P,*-ONE) ; Length of variable table

; Ending address of program so its length can be calculated for bootstrapping
; The constants defined after this are NOT initialized, so need not be 
;    downloaded. 

END_ADR	EQU	@LCV(L)		; End address of P: code written to ROM


NUM_GATHER	DC	0	; Number of image blocks
SV_A		DC	0	; Place for saving accumulator A
SV_A0		DC	0	; Accumulator A in interrupt service routine
SV_A1		DC	0
SV_X0		DC	0	; Data register X in interrupt service routine	
SV_X1		DC	0

; Scatter/Gather image writing variables
IBLK_SCATTER	DC	0	; Number of block being scattered, up counter
IBLK_GATHER 	DC	0	; Number of block being gathered, up counter
IRDFIFO		DC	0	; Index of 512 pixel chunks in FIFO
IPXLS_SCATTER_1	DC 	0	; Down Counter of number of pixels scattered
IPXLS_SCATTER_0	DC 	0	; Down Counter of number of pixels scattered
IPXLS_GATHER_1	DC 	0	; Down Counter of number of pixels gathered
IPXLS_GATHER_0	DC 	0	; Down Counter of number of pixels gathered

; Check that the parameter table is not too big
        IF	@CVS(N,*)>ARG_TBL
        WARN    'The parameter table is too big!'
	ENDIF

	ORG	X:ARG_TBL,P:

; Table that contains the command arguments		    PCI address
COMMAND_MSW	DC	0	; Manual command		$20	
COMMAND_LSW	DC	0	; Most significant word
NUM_ARG		DC	0	; Number of command arguments	$24
COM_DEST	DC	0	; Command destination		
ARG1_MSW	DC	0	; First command argument 	$28
ARG1_LSW	DC	0 
ARG2_MSW	DC	0	; Second command argument 	$2C
ARG2_LSW	DC	0 
ARG3_MSW	DC	0	; Third command argument 	$30
ARG3_LSW	DC	0 
ARG4_MSW	DC	0	; Fourth command argument 	$34
ARG4_LSW	DC	0
ARG5_MSW	DC	0	; Fifth command argument 	$38
ARG5_LSW	DC	0 
	 	DC	0	; Reserved 			$3C
	 	DC	0
ADR_BLOCK_0_B1	DC	0	; Block #1 address		$40
ADR_BLOCK_0_B0	DC	0
ADR_BLOCK_1_B1	DC	0	; Block #2 address 		$44
ADR_BLOCK_1_B0	DC	0
;						$48 - $7C are available
; Check that the argument table is not too big
	IF	@CVS(N,*)>TIM_TBL
        WARN    'The argument table is too big!'
	ENDIF

	ORG	X:TIM_TBL,P:							    
; Timing board table - 64 locations maximum = $100 bytes    PCI address
EXPTIME		DC	0	; Exposure time in millisec	$80
TIM_STAT	DC	0	; Controller options		$84
CAM_STATUS	DC	0	; Dummy in timing code		$88
NCOLS		DC	0	; Number of columns in image	$8C
NROWS		DC	0	; Number of rows in image	$90
NCBIN		DC	0	; Number of columns binned	$94
NRBIN		DC	0	; Number of rows binned		$98
UNUSED0		DC	0		
UNUSED1		DC	0
UNUSED2		DC	0
UNUSED3		DC	0
UNUSED4		DC	0
UNUSED5		DC	0
UNUSED6		DC	0

; Check that the timing table is not too big
        IF	@CVS(N,*)>TIM_TBL+TIM_LEN/4
        WARN    'The timing table is too big!'
	ENDIF

; **********************************************************************

; SCATTER / GATHER - Block addressing table

; bit #:   23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

;          ----------  Block Number 23 to 2  -----------------------   Busy

; The table has 254 entries to manage the 16 Mpixel image memory in blocks
;   that are each 65k pixels in size. Each entry of the table occupies one
;   24-bit DSP memory word.

; Busy : 	Set if the block is currently being read from or written to
; Block number - 23-bit block number in image of image data written
;
; If Busy = 1 then the block is currently being written to or read from
;   and must not be accessed except by its owner. 	
; If block number = Busy = 0 then the block is available for writing
;   FIFO data into it.
; If block number .NE. 0 then it contains FIFO data and should be written
;   to the host in order of block numbers. 
;
; **********************************************************************

	ORG	X:SC_TBL,P:

X_TABLE	DC	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0	; $80 locations for SG Table
	DUP	7
	DC	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
	ENDM
; **********************************************************************

; End of program
	END