; Miscellaneous definitions VID0 EQU $000000 ; Video board select = 0 VID1 EQU $001000 ; Video board select = 1 CLK2 EQU $002000 ; Select bottom of clock driver board CLK3 EQU $003000 ; Select top of clock driver board CLK4 EQU $004000 ; Select bottom of DC bias board CLK5 EQU $005000 ; Select top of DC bias board AD EQU $000001 ; Bit to start A/D conversion XFER EQU $000002 ; Bit to transfer A/D counts into the A/D FIFO SXMIT EQU $00F060 ; Transmit 4 pixels from the first coadder board ;SXMIT EQU $00F0E0 ; Transmit 8 pixels from the 2 coadder boards ; Various delay parameters ;DLY_AD EQU $100000 ; A/D convert pulse delay (320ns) DLY_AD EQU $000000 ; null A/D convert pulse delay DLY_AD1 EQU $0D0000 ; A/D convert pulse delay (260ns) - Need to use this one for the LAST_TWO_PIX waveform DLY0 EQU $000000 ; null delay ;DLY2 EQU $B20000 ; a full 8us delay - use this for 304 to get a 10+1.2us total pixel time ;DLY2 EQU $B60000 ; a 8.64us delay - use this for 304 to get a 10+1.2us total pixel time DLY2 EQU $AC0000 ; a 7.04us delay - use this for 304 to get a 10.0us total pixel time DLY3 EQU $FF0000 ; 20.4us delay (max delay) DLY4 EQU $150000 ; Burst-mode delay, for subarrays (500ns) DLY5 EQU $8C0000 ; 2 us underlap delay DLY6 EQU $820000 ; 400 ns delay DLY7 EQU $AE0000 ; 7.440us delay ; Put all the waveform tables in SRAM IF @SCP("DOWNLOAD","HOST") ORG Y:$100,Y:$100 ; Download address ELSE ORG Y:$100,P:APL_NUM*N_W_APL+APL_LEN+$340 ; ROM address ENDIF ; Define switch state bits for CLK2 = "bottom" of clock board and CLK3 = "top" of clock board, PC1 EQU 1 ; (pin 1, CLK2) Column shift register, phase 1 PIN2 EQU 2 ; (pin 2, CLK2) PR1 EQU 4 ; (pin 3, CLK2) Row shift register, phase 1 PR2 EQU 8 ; (pin 4, CLK2) Row shift register, phase 2 PC2 EQU $10 ; (pin 5, CLK2) Column shift register, phase 2 PIN6 EQU $20 ; (pin 6, CLK2) PIN7 EQU $40 ; (pin 7, CLK2) PIN8 EQU $80 ; (pin 8, CLK2) PIN9 EQU $100 ; (pin 9, CLK2) PIN10 EQU $200 ; (pin 10, CLK2) PIN11 EQU $400 ; (pin 11, CLK2) PIN12 EQU $800 ; (pin 12, CLK2) PIN13 EQU 1 ; (pin 13, CLK3) PIN14 EQU 2 ; (pin 14, CLK3) PIN15 EQU 4 ; (pin 15, CLK3) PIN16 EQU 8 ; (pin 16, CLK3) PIN17 EQU $10 ; (pin 17, CLK3) PIN18 EQU $20 ; (pin 18, CLK3) PIN19 EQU $40 ; (pin 19, CLK3) PIN33 EQU $80 ; (pin 33, CLK3) PIN34 EQU $100 ; (pin 34, CLK3) PIN35 EQU $200 ; (pin 35, CLK3) PSCANCOL EQU $400 ; (pin 36, CLK3) Control register scan direction PRST EQU $800 ; (pin 37, CLK3) Row reset clock (aka PRSTON and PRSTR) ; Define switch state bits for CLK4 = "bottom" of bias board and CLK5 = "top" of bias board, B_PIN1 EQU 1 ; (pin 1, CLK4) B_PIN2 EQU 2 ; (pin 2, CLK4) B_PIN3 EQU 4 ; (pin 3, CLK4) B_PIN4 EQU 8 ; (pin 4, CLK4) B_PIN5 EQU $10 ; (pin 5, CLK4) B_PIN6 EQU $20 ; (pin 6, CLK4) B_PIN7 EQU $40 ; (pin 7, CLK4) B_PIN8 EQU $80 ; (pin 8, CLK4) B_PIN9 EQU $100 ; (pin 9, CLK4) B_PIN10 EQU $200 ; (pin 10, CLK4) B_PIN11 EQU $400 ; (pin 11, CLK4) B_PIN12 EQU $800 ; (pin 12, CLK4) B_PIN13 EQU 1 ; (pin 13, CLK5) B_PIN14 EQU 2 ; (pin 14, CLK5) VSS2 EQU 4 ; (pin 15, CLK5) VSSOUT2 - active low VSS4 EQU 8 ; (pin 16, CLK5) VSSOUT4 - active low B_PIN17 EQU $10 ; (pin 17, CLK5) B_PIN18 EQU $20 ; (pin 18, CLK5) B_PIN19 EQU $40 ; (pin 19, CLK5) VSS1 EQU $80 ; (pin 33, CLK5) VSSOUT1 - active low VSS3 EQU $100 ; (pin 34, CLK5) VSSOUT3 - active low VRSTOFF EQU $200 ; (pin 35, CLK5) High clock for row rest FETs (Global reset enable?) VROWON EQU $400 ; (pin 36, CLK5) row FET enable B_PIN37 EQU $800 ; (pin 37, CLK5) ; set default pixel sample time (This should usually match DLY2 in waveforms.asm) PIX_TIM DC DLY2 ; pixel clock time, written by host computer (10us default here) ; Copy of the clocking bit definition for easy reference. ; DC CLK2+DLY2+PC1+PR1+PR2+PC2 ; DC CLK3+DLY2+PSCANCOL+PRST ; DC CLK5+DLY2+VROWON+VRSTOFF+VSS1+VSS2+VSS3+VSS4 WAVE_START DC WAVE_END-WAVE_START-2 ; Total number of waves in the table FRAME_INIT DC END_FRAME_INIT-FRAME_INIT-2 DC CLK5+DLY0+VROWON+0000000 ; VROWON HI (also turns VSS* on) DC CLK2+DLY2+PC1+PR1+PR2+PC2 ; send all clocks HI for FSYNC DC CLK2+DLY2+PC1+PR1+000+000 ; Then send PR2, PC2 LO END_FRAME_INIT CLOCK_ROW_ODD DC END_CLOCK_ROW_ODD-CLOCK_ROW_ODD-2 ; DC CLK3+DLY0+PSCANCOL+0000 ; just for testing ; DC CLK3+DLY0+00000000+0000 ; just for testing DC CLK2+DLY5+PC1+000+000+000 ; PR1 LO, PR2 LO DC CLK2+DLY5+PC1+000+PR2+000 ; PR1 LO, PR2 HI (selects next row) DC CLK2+DLY5+PC1+000+PR2+PC2 ; Pulse PC2 HI to sync DC CLK2+DLY5+PC1+000+PR2+000 ; PC2 LO (now PC1 is HI PC2 is LO) END_CLOCK_ROW_ODD CLOCK_ROW_ODD_LONG DC END_CLOCK_ROW_ODD_LONG-CLOCK_ROW_ODD_LONG-2 DC CLK2+DLY5+PC1+000+000+000 ; PR1 LO, PR2 LO DC CLK2+DLY3+PC1+000+PR2+000 ; PR1 LO, PR2 HI (selects next row) DC CLK2+DLY3+PC1+000+PR2+000 ; DC CLK2+DLY3+PC1+000+PR2+000 ; DC CLK2+DLY3+PC1+000+PR2+000 ; DC CLK2+DLY3+PC1+000+PR2+000 ; DC CLK2+DLY5+PC1+000+PR2+PC2 ; Pulse PC2 HI to sync DC CLK2+DLY5+PC1+000+PR2+000 ; PC2 LO (now PC1 is HI PC2 is LO) END_CLOCK_ROW_ODD_LONG CLOCK_ROW_ODD_FAST DC END_CLOCK_ROW_ODD_FAST-CLOCK_ROW_ODD_FAST-2 DC CLK2+DLY5+PC1+000+000+000 ; PR1 LO, PR2 LO DC CLK2+DLY5+PC1+000+PR2+000 ; PR1 LO, PR2 HI (selects next row) END_CLOCK_ROW_ODD_FAST CLOCK_ROW_ODD_RESET DC END_CLOCK_ROW_ODD_RESET-CLOCK_ROW_ODD_RESET-2 DC CLK2+DLY5+PC1+000+000+000 ; PR1 LO, PR2 LO DC CLK2+DLY5+PC1+000+PR2+000 ; PR1 LO, PR2 HI (selects next row) DC CLK5+DLY6+000000+000000 ; send VROWON LO DC CLK3+DLY2+00000000+PRST ; Pulse reset for 1 pixel time DC CLK3+DLY6+00000000+0000 DC CLK5+DLY5+VROWON+000000 ; VROWON back HI END_CLOCK_ROW_ODD_RESET RESET_ON DC END_RESET_ON-RESET_ON-2 DC CLK5+DLY3+000000+000000 ; send VROWON LO, wait ~100 us DC CLK5+DLY3+000000+000000 DC CLK5+DLY3+000000+000000 DC CLK5+DLY3+000000+000000 DC CLK5+DLY3+000000+000000 DC CLK3+DLY3+00000000+PRST ; send PRST HI, wait ~100us DC CLK3+DLY3+00000000+PRST DC CLK3+DLY3+00000000+PRST DC CLK3+DLY3+00000000+PRST DC CLK3+DLY3+00000000+PRST END_RESET_ON RESET_OFF DC END_RESET_OFF-RESET_OFF-2 DC CLK3+DLY3+00000000+0000 ; send PRST LO, wait ~20us (2 time const, is enough to get it mostly off before setting VROWON HI) DC CLK5+DLY3+VROWON+000000 ; send VROWON HI, wait ~100 us DC CLK5+DLY3+VROWON+000000 DC CLK5+DLY3+VROWON+000000 DC CLK5+DLY3+VROWON+000000 DC CLK5+DLY3+VROWON+000000 END_RESET_OFF CLOCK_ROW_EVEN DC END_CLOCK_ROW_EVEN-CLOCK_ROW_EVEN-2 DC CLK2+DLY5+PC1+000+000+000 ; PR1 LO, PR2 LO DC CLK2+DLY5+PC1+PR1+000+000 ; PR1 HI, PR2 LO (selects next row) DC CLK2+DLY5+PC1+PR1+000+PC2 ; Pulse PC2 HI to sync DC CLK2+DLY5+PC1+PR1+000+000 ; PC2 LO (now PC1 is HI PC2 is LO) END_CLOCK_ROW_EVEN CLOCK_ROW_EVEN_LONG DC END_CLOCK_ROW_EVEN_LONG-CLOCK_ROW_EVEN_LONG-2 DC CLK2+DLY5+PC1+000+000+000 ; PR1 LO, PR2 LO DC CLK2+DLY3+PC1+PR1+000+000 ; PR1 HI, PR2 LO (selects next row) DC CLK2+DLY3+PC1+PR1+000+000 ; DC CLK2+DLY3+PC1+PR1+000+000 ; DC CLK2+DLY3+PC1+PR1+000+000 ; DC CLK2+DLY3+PC1+PR1+000+000 ; DC CLK2+DLY5+PC1+PR1+000+PC2 ; Pulse PC2 HI to sync DC CLK2+DLY5+PC1+PR1+000+000 ; PC2 LO (now PC1 is HI PC2 is LO) END_CLOCK_ROW_EVEN_LONG CLOCK_ROW_EVEN_FAST DC END_CLOCK_ROW_EVEN_FAST-CLOCK_ROW_EVEN_FAST-2 DC CLK2+DLY5+PC1+000+000+000 ; PR1 LO, PR2 LO DC CLK2+DLY5+PC1+PR1+000+000 ; PR1 HI, PR2 LO (selects next row) END_CLOCK_ROW_EVEN_FAST CLOCK_ROW_EVEN_RESET DC END_CLOCK_ROW_EVEN_RESET-CLOCK_ROW_EVEN_RESET-2 DC CLK2+DLY5+PC1+000+000+000 ; PR1 LO, PR2 LO DC CLK2+DLY5+PC1+PR1+000+000 ; PR1 HI, PR2 LO (selects next row) DC CLK5+DLY6+VROWON+000000 ; these are do-nothings DC CLK3+DLY2+00000000+0000 ; to match the odd row timing DC CLK3+DLY6+00000000+0000 DC CLK5+DLY5+VROWON+000000 ; these are do-nothings END_CLOCK_ROW_EVEN_RESET ; **************************************************************************************************************** ; PT => Pass Through mode, wherein the coadder boards pass pixel data as ; quickly as possible to the timing board for transmission to the host ; same as non-pt, but with a different delay. CLOCK_COL_AND_READ_ODD_PT_OC ; this clocks and reads 1 pix at a time, for an odd row DC END_CLOCK_COL_AND_READ_ODD_PT_OC-CLOCK_COL_AND_READ_ODD_PT_OC-2 DC VID0+DLY7 ; DC CLK3+DLY0+PSCANCOL+0000 ; just for testing ; DC CLK3+DLY0+00000000+0000 ; just for testing DC VID0+DLY_AD+AD+XFER ; now clock to the next pixel before the XFER (after the full hold delay on the A/D - 720ns) ; next pix will be an ODD_PT_EC DC CLK2+DLY6+000+000+PR2+000 ; PC1 LO, PC2 LO DC CLK2+DLY0+PC1+000+PR2+000 ; PC1 HI, PC2 LO DC VID0 ; send AD back LO DC SXMIT END_CLOCK_COL_AND_READ_ODD_PT_OC CLOCK_COL_AND_READ_ODD_PT_EC_DELAY ; this clocks and reads 1 pix at a time, for an odd row (This one has the ref pixel delay of 4 pixel times) DC END_CLOCK_COL_AND_READ_ODD_PT_EC_DELAY-CLOCK_COL_AND_READ_ODD_PT_EC_DELAY-2 DC CLK2+DLY3+PC1+000+PR2+000 ; PC1 HI, PC2 LO ; send this wave 2 times to get 40us delay DC CLK2+DLY3+PC1+000+PR2+000 ; PC1 HI, PC2 LO ; DC CLK3+DLY0+PSCANCOL+0000 ; just for testing ; DC CLK3+DLY0+00000000+0000 ; just for testing DC VID0+DLY_AD+AD+XFER ; now clock to the next pixel before the XFER (after the full hold delay on the A/D - 720ns) ; next pix will be an ODD_PT_OC DC CLK2+DLY6+000+000+PR2+000 ; PC1 LO, PC2 LO DC CLK2+DLY0+000+000+PR2+PC2 ; PC1 LO, PC2 HI DC VID0 ; send AD back LO DC SXMIT END_CLOCK_COL_AND_READ_ODD_PT_EC_DELAY CLOCK_COL_AND_READ_ODD_PT_EC ; this clocks and reads 1 pix at a time, for an odd row DC END_CLOCK_COL_AND_READ_ODD_PT_EC-CLOCK_COL_AND_READ_ODD_PT_EC-2 DC VID0+DLY7 ; DC CLK3+DLY0+PSCANCOL+0000 ; just for testing ; DC CLK3+DLY0+00000000+0000 ; just for testing DC VID0+DLY_AD+AD+XFER ; now clock to the next pixel before the XFER (after the full hold delay on the A/D - 720ns) ; next pix will be an ODD_PT_OC DC CLK2+DLY6+000+000+PR2+000 ; PC1 LO, PC2 LO DC CLK2+DLY0+000+000+PR2+PC2 ; PC1 LO, PC2 HI DC VID0 ; send AD back LO DC SXMIT END_CLOCK_COL_AND_READ_ODD_PT_EC CLOCK_COL_AND_READ_EVEN_PT_OC ; this clocks and reads 1 pix at a time, for an even row DC END_CLOCK_COL_AND_READ_EVEN_PT_OC-CLOCK_COL_AND_READ_EVEN_PT_OC-2 DC VID0+DLY7 DC VID0+DLY_AD+AD+XFER ; now clock to the next pixel before the XFER (after the full hold delay on the A/D - 720ns) ; next pix will be an EVEN_PT_EC DC CLK2+DLY6+000+PR1+000+000 ; PC1 LO, PC2 LO DC CLK2+DLY0+PC1+PR1+000+000 ; PC1 HI, PC2 LO DC VID0 ; send AD back LO DC SXMIT END_CLOCK_COL_AND_READ_EVEN_PT_OC CLOCK_COL_AND_READ_EVEN_PT_EC_DELAY ; this clocks and reads 1 pix at a time, for an even row (This one has the ref pixel delay of 4 pixel times) DC END_CLOCK_COL_AND_READ_EVEN_PT_EC_DELAY-CLOCK_COL_AND_READ_EVEN_PT_EC_DELAY-2 DC CLK2+DLY3+PC1+PR1+000+000 ; PC1 HI, PC2 LO ; send this wave 2 times to get 40us delay DC CLK2+DLY3+PC1+PR1+000+000 ; PC1 HI, PC2 LO DC VID0+DLY_AD+AD+XFER ; now clock to the next pixel before the XFER (after the full hold delay on the A/D - 720ns) ; next pix will be an EVEN_PT_OC DC CLK2+DLY6+000+PR1+000+000 ; PC1 LO, PC2 LO DC CLK2+DLY0+000+PR1+000+PC2 ; PC1 LO, PC2 HI DC VID0 ; send AD back LO DC SXMIT END_CLOCK_COL_AND_READ_EVEN_PT_EC_DELAY CLOCK_COL_AND_READ_EVEN_PT_EC ; this clocks and reads 1 pix at a time, for an even row DC END_CLOCK_COL_AND_READ_EVEN_PT_EC-CLOCK_COL_AND_READ_EVEN_PT_EC-2 DC VID0+DLY7 DC VID0+DLY_AD+AD+XFER ; now clock to the next pixel before the XFER (after the full hold delay on the A/D - 720ns) ; next pix will be an EVEN_PT_OC DC CLK2+DLY6+000+PR1+000+000 ; PC1 LO, PC2 LO DC CLK2+DLY0+000+PR1+000+PC2 ; PC1 LO, PC2 HI DC VID0 ; send AD back LO DC SXMIT END_CLOCK_COL_AND_READ_EVEN_PT_EC CLOCK_COL_AND_READ_ODD_PT_NO_XFER_OC_DELAY ; this clocks and reads 1 pix at a time, for an odd row (This one has the ref pixel delay of 4 pixel times) DC END_CLOCK_COL_AND_READ_ODD_PT_NO_XFER_OC_DELAY-CLOCK_COL_AND_READ_ODD_PT_NO_XFER_OC_DELAY-2 DC CLK2+DLY6+000+000+PR2+000 ; PC1 LO, PC2 LO DC CLK2+DLY3+000+000+PR2+PC2 ; PC1 LO, PC2 HI ; send this wave 2 times to get 40us delay DC CLK2+DLY3+000+000+PR2+PC2 ; PC1 LO, PC2 HI ; DC CLK3+DLY0+PSCANCOL+0000 ; just for testing ; DC CLK3+DLY0+00000000+0000 ; just for testing DC VID0+DLY_AD+AD ; now clock to the next pixel before the XFER (after the full hold delay on the A/D - 720ns) ; next pix will be an ODD_PT_EC DC CLK2+DLY6+000+000+PR2+000 ; PC1 LO, PC2 LO DC CLK2+DLY0+PC1+000+PR2+000 ; PC1 HI, PC2 LO DC VID0 ; send AD back LO DC VID0 ; this is a do-nothing placeholder for the SXMIT which is normally here END_CLOCK_COL_AND_READ_ODD_PT_NO_XFER_OC_DELAY CLOCK_COL_AND_READ_ODD_PT_NO_XFER_OC ; this clocks and reads 1 pix at a time, for an odd row DC END_CLOCK_COL_AND_READ_ODD_PT_NO_XFER_OC-CLOCK_COL_AND_READ_ODD_PT_NO_XFER_OC-2 DC VID0+DLY7 DC VID0+DLY_AD+AD ; now clock to the next pixel before the XFER (after the full hold delay on the A/D - 720ns) ; next pix will be an ODD_PT_EC DC CLK2+DLY6+000+000+PR2+000 ; PC1 LO, PC2 LO DC CLK2+DLY0+PC1+000+PR2+000 ; PC1 HI, PC2 LO DC VID0 ; send AD back LO DC VID0 ; this is a do-nothing placeholder for the SXMIT which is normally here END_CLOCK_COL_AND_READ_ODD_PT_NO_XFER_OC CLOCK_COL_AND_READ_ODD_PT_NO_XFER_EC ; this clocks and reads 1 pix at a time, for an odd row DC END_CLOCK_COL_AND_READ_ODD_PT_NO_XFER_EC-CLOCK_COL_AND_READ_ODD_PT_NO_XFER_EC-2 DC VID0+DLY7 DC VID0+DLY_AD+AD ; now clock to the next pixel before the XFER (after the full hold delay on the A/D - 720ns) ; next pix will be an ODD_PT_OC DC CLK2+DLY6+000+000+PR2+000 ; PC1 LO, PC2 LO DC CLK2+DLY0+000+000+PR2+PC2 ; PC1 LO, PC2 HI DC VID0 ; send AD back LO DC VID0 ; this is a do-nothing placeholder for the SXMIT which is normally here END_CLOCK_COL_AND_READ_ODD_PT_NO_XFER_EC CLOCK_COL_AND_READ_EVEN_PT_NO_XFER_OC ; this clocks and reads 1 pix at a time, for an even row DC END_CLOCK_COL_AND_READ_EVEN_PT_NO_XFER_OC-CLOCK_COL_AND_READ_EVEN_PT_NO_XFER_OC-2 DC VID0+DLY7 DC VID0+DLY_AD+AD ; now clock to the next pixel before the XFER (after the full hold delay on the A/D - 720ns) ; next pix will be an EVEN_PT_EC DC CLK2+DLY6+000+PR1+000+000 ; PC1 LO, PC2 LO DC CLK2+DLY0+PC1+PR1+000+000 ; PC1 HI, PC2 LO DC VID0 ; send AD back LO DC VID0 ; this is a do-nothing placeholder for the SXMIT which is normally here END_CLOCK_COL_AND_READ_EVEN_PT_NO_XFER_OC CLOCK_COL_AND_READ_EVEN_PT_NO_XFER_OC_DELAY ; this clocks and reads 1 pix at a time, for an even row (This one has the ref pixel delay of 4 pixel times) DC END_CLOCK_COL_AND_READ_EVEN_PT_NO_XFER_OC_DELAY-CLOCK_COL_AND_READ_EVEN_PT_NO_XFER_OC_DELAY-2 DC CLK2+DLY6+000+PR1+000+000 ; PC1 LO, PC2 LO DC CLK2+DLY3+000+PR1+000+PC2 ; PC1 LO, PC2 HI ; send this wave 2 times to get 40us delay DC CLK2+DLY3+000+PR1+000+PC2 ; PC1 LO, PC2 HI ; DC CLK3+DLY0+PSCANCOL+0000 ; just for testing ; DC CLK3+DLY0+00000000+0000 ; just for testing DC VID0+DLY_AD+AD ; now clock to the next pixel before the XFER (after the full hold delay on the A/D - 720ns) ; next pix will be an EVEN_PT_EC DC CLK2+DLY6+000+PR1+000+000 ; PC1 LO, PC2 LO DC CLK2+DLY0+PC1+PR1+000+000 ; PC1 HI, PC2 LO DC VID0 ; send AD back LO DC VID0 ; this is a do-nothing placeholder for the SXMIT which is normally here END_CLOCK_COL_AND_READ_EVEN_PT_NO_XFER_OC_DELAY CLOCK_COL_AND_READ_EVEN_PT_NO_XFER_EC ; this clocks and reads 1 pix at a time, for an even row DC END_CLOCK_COL_AND_READ_EVEN_PT_NO_XFER_EC-CLOCK_COL_AND_READ_EVEN_PT_NO_XFER_EC-2 DC VID0+DLY7 DC VID0+DLY_AD+AD ; now clock to the next pixel before the XFER (after the full hold delay on the A/D - 720ns) ; next pix will be an EVEN_PT_OC DC CLK2+DLY6+000+PR1+000+000 ; PC1 LO, PC2 LO DC CLK2+DLY0+000+PR1+000+PC2 ; PC1 LO, PC2 HI DC VID0 ; send AD back LO DC VID0 ; this is a do-nothing placeholder for the SXMIT which is normally here END_CLOCK_COL_AND_READ_EVEN_PT_NO_XFER_EC ; **************************************************************************************************************** ; **************************************************************************************************************** ; The second waveform table here does A/D conversion without writing ; The A/D values to the latch with XFER. The first waveform table does ; the A/D conversion and writes the previous A/D value to the latch ; because of the pipeline delay in the ADS937 A/D converter. CLOCK_COL_AND_READ_ODD_OC ; this clocks and reads 1 pix at a time, for an odd row DC END_CLOCK_COL_AND_READ_ODD_OC-CLOCK_COL_AND_READ_ODD_OC-2 DC CLK2+DLY6+000+000+PR2+000 ; PC1 LO, PC2 LO DC CLK2+DLY2+000+000+PR2+PC2 ; PC1 LO, PC2 HI DC VID0+DLY_AD+AD+XFER DC VID0 END_CLOCK_COL_AND_READ_ODD_OC CLOCK_COL_AND_READ_ODD_EC_DELAY ; this clocks and reads 1 pix at a time, for an odd row (This one has the ref pixel delay of 4 pixel times) DC END_CLOCK_COL_AND_READ_ODD_EC_DELAY-CLOCK_COL_AND_READ_ODD_EC_DELAY-2 DC CLK2+DLY6+000+000+PR2+000 ; PC1 LO, PC2 LO DC CLK2+DLY3+PC1+000+PR2+000 ; PC1 HI, PC2 LO ; send this wave 2 times to get 40us delay DC CLK2+DLY3+PC1+000+PR2+000 ; PC1 HI, PC2 LO DC VID0+DLY_AD+AD+XFER DC VID0 END_CLOCK_COL_AND_READ_ODD_EC_DELAY CLOCK_COL_AND_READ_ODD_EC ; this clocks and reads 1 pix at a time, for an odd row DC END_CLOCK_COL_AND_READ_ODD_EC-CLOCK_COL_AND_READ_ODD_EC-2 DC CLK2+DLY6+000+000+PR2+000 ; PC1 LO, PC2 LO DC CLK2+DLY2+PC1+000+PR2+000 ; PC1 HI, PC2 LO DC VID0+DLY_AD+AD+XFER DC VID0 END_CLOCK_COL_AND_READ_ODD_EC CLOCK_COL_AND_READ_EVEN_OC ; this clocks and reads 1 pix at a time, for an even row DC END_CLOCK_COL_AND_READ_EVEN_OC-CLOCK_COL_AND_READ_EVEN_OC-2 DC CLK2+DLY6+000+PR1+000+000 ; PC1 LO, PC2 LO DC CLK2+DLY2+000+PR1+000+PC2 ; PC1 LO, PC2 HI DC VID0+DLY_AD+AD+XFER DC VID0 END_CLOCK_COL_AND_READ_EVEN_OC CLOCK_COL_AND_READ_EVEN_EC_DELAY ; this clocks and reads 1 pix at a time, for an even row (This one has the ref pixel delay of 4 pixel times) DC END_CLOCK_COL_AND_READ_EVEN_EC_DELAY-CLOCK_COL_AND_READ_EVEN_EC_DELAY-2 DC CLK2+DLY6+000+PR1+000+000 ; PC1 LO, PC2 LO DC CLK2+DLY3+PC1+PR1+000+000 ; PC1 HI, PC2 LO ; send this wave 2 times to get 40us delay DC CLK2+DLY3+PC1+PR1+000+000 ; PC1 HI, PC2 LO DC VID0+DLY_AD+AD+XFER DC VID0 END_CLOCK_COL_AND_READ_EVEN_EC_DELAY CLOCK_COL_AND_READ_EVEN_EC ; this clocks and reads 1 pix at a time, for an even row DC END_CLOCK_COL_AND_READ_EVEN_EC-CLOCK_COL_AND_READ_EVEN_EC-2 DC CLK2+DLY6+000+PR1+000+000 ; PC1 LO, PC2 LO DC CLK2+DLY2+PC1+PR1+000+000 ; PC1 HI, PC2 LO DC VID0+DLY_AD+AD+XFER DC VID0 END_CLOCK_COL_AND_READ_EVEN_EC CLOCK_COL_AND_READ_ODD_NO_XFER_OC_DELAY ; this clocks and reads 1 pix at a time, for an odd row (This one has the ref pixel delay of 4 pixel times) DC END_CLOCK_COL_AND_READ_ODD_NO_XFER_OC_DELAY-CLOCK_COL_AND_READ_ODD_NO_XFER_OC_DELAY-2 DC CLK2+DLY6+000+000+PR2+000 ; PC1 LO, PC2 LO DC CLK2+DLY3+000+000+PR2+PC2 ; PC1 LO, PC2 HI ; send this wave 2 times to get 40us delay DC CLK2+DLY3+000+000+PR2+PC2 ; PC1 LO, PC2 HI DC VID0+DLY_AD+AD DC VID0 END_CLOCK_COL_AND_READ_ODD_NO_XFER_OC_DELAY CLOCK_COL_AND_READ_ODD_NO_XFER_OC ; this clocks and reads 1 pix at a time, for an odd row DC END_CLOCK_COL_AND_READ_ODD_NO_XFER_OC-CLOCK_COL_AND_READ_ODD_NO_XFER_OC-2 DC CLK2+DLY6+000+000+PR2+000 ; PC1 LO, PC2 LO DC CLK2+DLY2+000+000+PR2+PC2 ; PC1 LO, PC2 HI DC VID0+DLY_AD+AD DC VID0 END_CLOCK_COL_AND_READ_ODD_NO_XFER_OC CLOCK_COL_AND_READ_ODD_NO_XFER_EC ; this clocks and reads 1 pix at a time, for an odd row DC END_CLOCK_COL_AND_READ_ODD_NO_XFER_EC-CLOCK_COL_AND_READ_ODD_NO_XFER_EC-2 DC CLK2+DLY6+000+000+PR2+000 ; PC1 LO, PC2 LO DC CLK2+DLY2+PC1+000+PR2+000 ; PC1 HI, PC2 LO DC VID0+DLY_AD+AD DC VID0 END_CLOCK_COL_AND_READ_ODD_NO_XFER_EC CLOCK_COL_AND_READ_EVEN_NO_XFER_OC_DELAY ; this clocks and reads 1 pix at a time, for an even row (This one has the ref pixel delay of 4 pixel times) DC END_CLOCK_COL_AND_READ_EVEN_NO_XFER_OC_DELAY-CLOCK_COL_AND_READ_EVEN_NO_XFER_OC_DELAY-2 DC CLK2+DLY6+000+PR1+000+000 ; PC1 LO, PC2 LO DC CLK2+DLY3+000+PR1+000+PC2 ; PC1 LO, PC2 HI ; send this wave 2 times to get 40us delay DC CLK2+DLY3+000+PR1+000+PC2 ; PC1 LO, PC2 HI DC VID0+DLY_AD+AD DC VID0 END_CLOCK_COL_AND_READ_EVEN_NO_XFER_OC_DELAY CLOCK_COL_AND_READ_EVEN_NO_XFER_OC ; this clocks and reads 1 pix at a time, for an even row DC END_CLOCK_COL_AND_READ_EVEN_NO_XFER_OC-CLOCK_COL_AND_READ_EVEN_NO_XFER_OC-2 DC CLK2+DLY6+000+PR1+000+000 ; PC1 LO, PC2 LO DC CLK2+DLY2+000+PR1+000+PC2 ; PC1 LO, PC2 HI DC VID0+DLY_AD+AD DC VID0 END_CLOCK_COL_AND_READ_EVEN_NO_XFER_OC CLOCK_COL_AND_READ_EVEN_NO_XFER_EC ; this clocks and reads 1 pix at a time, for an even row DC END_CLOCK_COL_AND_READ_EVEN_NO_XFER_EC-CLOCK_COL_AND_READ_EVEN_NO_XFER_EC-2 DC CLK2+DLY6+000+PR1+000+000 ; PC1 LO, PC2 LO DC CLK2+DLY2+PC1+PR1+000+000 ; PC1 HI, PC2 LO DC VID0+DLY_AD+AD DC VID0 END_CLOCK_COL_AND_READ_EVEN_NO_XFER_EC ; **************************************************************************************************************** ; These two waveforms tables only do A/D conversions and transfers of ; latched data to the FIFOs. This is executed at the end of reading ; the array to get the last A/D values left over because of the ; pipeline delay. Note that the blocks here only do a single A/D convert. ; Must execute this twice to get two pixels. READ_LAST_TWO_PIXELS DC END_READ_LAST_TWO_PIXELS-READ_LAST_TWO_PIXELS-2 DC VID0 ; AD off DC VID0+DLY_AD1+AD+XFER ; AD on and transfer DC VID0 ; AD off DC VID0 END_READ_LAST_TWO_PIXELS SXMIT_LAST_TWO_PIXELS DC END_SXMIT_LAST_TWO_PIXELS-SXMIT_LAST_TWO_PIXELS-2 DC VID0 ; AD off DC VID0+DLY_AD1+AD+XFER ; AD on and transfer DC VID0 ; AD off DC SXMIT ; transmit to host END_SXMIT_LAST_TWO_PIXELS ; the following are primarily for BO mode and a few other activities ;********************************************************************************************** ; this is for advancing the pixel clock without an A2D conversion CLOCK_ONLY_ODD_OC ; this clocks and reads 2 pix at a time, for an odd row DC END_CLOCK_ONLY_ODD_OC-CLOCK_ONLY_ODD_OC-2 DC CLK2+DLY6+000+000+PR2+000 ; PC1 LO, PC2 LO DC CLK2+DLY2+000+000+PR2+PC2 ; PC1 LO, PC2 HI END_CLOCK_ONLY_ODD_OC CLOCK_ONLY_ODD_EC ; this clocks and reads 2 pix at a time, for an odd row DC END_CLOCK_ONLY_ODD_EC-CLOCK_ONLY_ODD_EC-2 DC CLK2+DLY6+000+000+PR2+000 ; PC1 LO, PC2 LO DC CLK2+DLY2+PC1+000+PR2+000 ; PC1 HI, PC2 LO END_CLOCK_ONLY_ODD_EC CLOCK_ONLY_ODD_FAST_OC ; this clocks and reads 2 pix at a time, for an odd row - as fast as possible for burst-mode subarray DC END_CLOCK_ONLY_ODD_FAST_OC-CLOCK_ONLY_ODD_FAST_OC-2 DC CLK2+DLY6+000+000+PR2+000 ; PC1 LO, PC2 LO DC CLK2+DLY4+000+000+PR2+PC2 ; PC1 LO, PC2 HI END_CLOCK_ONLY_ODD_FAST_OC CLOCK_ONLY_ODD_FAST_EC ; this clocks and reads 2 pix at a time, for an odd row - as fast as possible for burst-mode subarray DC END_CLOCK_ONLY_ODD_FAST_EC-CLOCK_ONLY_ODD_FAST_EC-2 DC CLK2+DLY6+000+000+PR2+000 ; PC1 LO, PC2 LO DC CLK2+DLY4+PC1+000+PR2+000 ; PC1 HI, PC2 LO END_CLOCK_ONLY_ODD_FAST_EC CLOCK_ONLY_EVEN_OC ; this clocks and reads 2 pix at a time, for an odd row DC END_CLOCK_ONLY_EVEN_OC-CLOCK_ONLY_EVEN_OC-2 DC CLK2+DLY6+000+PR1+000+000 ; PC1 LO, PC2 LO DC CLK2+DLY2+000+PR1+000+PC2 ; PC1 LO, PC2 HI END_CLOCK_ONLY_EVEN_OC CLOCK_ONLY_EVEN_EC ; this clocks and reads 2 pix at a time, for an odd row DC END_CLOCK_ONLY_EVEN_EC-CLOCK_ONLY_EVEN_EC-2 DC CLK2+DLY6+000+PR1+000+000 ; PC1 LO, PC2 LO DC CLK2+DLY2+PC1+PR1+000+000 ; PC1 HI, PC2 LO END_CLOCK_ONLY_EVEN_EC CLOCK_ONLY_EVEN_FAST_OC ; this clocks and reads 2 pix at a time, for an odd row - as fast as possible for burst-mode subarray DC END_CLOCK_ONLY_EVEN_FAST_OC-CLOCK_ONLY_EVEN_FAST_OC-2 DC CLK2+DLY6+000+PR1+000+000 ; PC1 LO, PC2 LO DC CLK2+DLY4+000+PR1+000+PC2 ; PC1 LO, PC2 HI END_CLOCK_ONLY_EVEN_FAST_OC CLOCK_ONLY_EVEN_FAST_EC ; this clocks and reads 2 pix at a time, for an odd row - as fast as possible for burst-mode subarray DC END_CLOCK_ONLY_EVEN_FAST_EC-CLOCK_ONLY_EVEN_FAST_EC-2 DC CLK2+DLY6+000+PR1+000+000 ; PC1 LO, PC2 LO DC CLK2+DLY4+PC1+PR1+000+000 ; PC1 HI, PC2 LO END_CLOCK_ONLY_EVEN_FAST_EC ; this is for an A2D conversion without advancing the pixel clock (with transfer) A2D_ONLY DC END_A2D_ONLY-A2D_ONLY-2 ; DC CLK3+DLY0+PSCANCOL+0000 ; just for testing ; DC CLK3+DLY0+00000000+0000 ; just for testing DC VID0+DLY_AD1+AD+XFER ; AD convert DC VID0 ; AD off DC SXMIT END_A2D_ONLY ; this is for an A2D conversion without advancing the pixel clock (NO transfer) A2D_ONLY_NO_XFER DC END_A2D_ONLY_NO_XFER-A2D_ONLY_NO_XFER-2 ; DC CLK3+DLY0+PSCANCOL+0000 ; just for testing ; DC CLK3+DLY0+00000000+0000 ; just for testing DC VID0+DLY_AD1+AD ; AD convert DC VID0 ; AD off DC VID0 END_A2D_ONLY_NO_XFER PULSE_GLOBAL_RESET ; this is just a guess right now DC END_PULSE_GLOBAL_RESET-PULSE_GLOBAL_RESET-2 DC CLK5+DLY5+VROWON+0000000 ; set VROWON HI DC CLK5+DLY3+VROWON+VRSTOFF ; global reset on, hold for 100 us DC CLK5+DLY3+VROWON+VRSTOFF ; DC CLK5+DLY3+VROWON+VRSTOFF ; DC CLK5+DLY3+VROWON+VRSTOFF ; DC CLK5+DLY3+VROWON+VRSTOFF ; DC CLK5+DLY3+VROWON+0000000 ; global reset off, hold for 40 us DC CLK5+DLY3+VROWON+0000000 ; DC CLK5+DLY0+VROWON+0000000 ; leave VROWON HI END_PULSE_GLOBAL_RESET VSOURCE_OFF ; don't need a VSOURCE_ON, since the FRAME_INIT takes care of that. ; just turn these off after each readout finishes. DC VSOURCE_OFF_END-VSOURCE_OFF-1 ; DC CLK5+DLY0+VROWON+00000 ; this will leave them on DC CLK5+DLY0+VROWON+00000+VSS1+VSS2+VSS3+VSS4 ; SET VSSOUT[1,2,3,4] and VROWON LO VSOURCE_OFF_END ;********************************************************************************************** WAVE_END ; Values for IR clock and bias boards. Both boards are jumpered for bipolar operation MAX_V EQU 7.5 ; Maximum voltage from bias driver board MAX_V2 EQU 15.0 ; 2 x MAX_V CLK_ZERO EQU 0.0 ; Zero volts for power-on sequence ; Zero out ALL the DC biases and clocks during the power-on sequence (zero all lines) ZERO_BIASES DC END_ZERO_BIASES-ZERO_BIASES-1 ; clock board DC (CLK2<<8)+(0<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(1<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(2<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(3<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(4<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(5<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(6<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(7<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(8<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(9<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(10<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(11<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(12<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(13<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(14<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(15<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(16<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(17<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(18<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(19<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(20<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(21<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(22<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(23<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(24<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(25<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(26<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(27<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(28<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(29<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(30<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(31<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(32<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(33<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(34<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(35<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(36<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(37<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(38<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(39<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(40<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(41<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(42<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(43<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(44<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(45<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(46<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(47<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; bias board DC (CLK4<<8)+(0<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(1<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(2<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(3<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(4<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(5<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(6<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(7<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(8<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(9<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(10<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(11<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(12<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(13<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(14<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(15<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(16<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(17<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(18<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(19<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(20<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(21<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(22<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(23<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(24<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(25<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(26<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(27<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(28<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(29<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(30<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(31<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(32<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(33<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(34<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(35<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(36<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(37<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(38<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(39<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(40<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(41<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(42<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(43<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(44<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(45<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(46<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(47<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) END_ZERO_BIASES ; Initialize all DACs ; Clocking voltage definitions ; set voltages using CLK2 0-47, just as if setting biases on CLK4, but remember that ; switch states for output lines 0-11 are CLK2 and ; switch states for output lines 12-23 are CLK3 ; Also, set any unused pins to zero here CLK_HI_1 EQU -5.0 ; High Clock voltage -5.6 CLK_HI_2 EQU -4.9 ; High Clock voltage CLK_HI_3 EQU -3.05 ; High Clock voltage -3.85 ;;;CLK_HI_3 EQU -0.1 ; High Clock voltage TESTING CLK_HI_4 EQU -3.85 ; VROWON CLK_LO_1 EQU -2.9 ; Low Clock voltage CLK_LO_2 EQU -0.35 ; Low Clock voltage ;;;CLK_LO_2 EQU 0.0 ; Low Clock voltage TESTING CLK_LO_4 EQU -1.0 ; VROWON ; Bias voltage definitions ; The DC bias board is strapped ; for bipolar outputs to accomodate the +1.0 volt VssOUT required for the video ; source followers. The rail voltage is MAX_V = 7.5 volts. MAX_V2 = 2 x MAX_V = 15.0 ; Also, set any unused pins to zero here VDETCOM EQU -2.9 ; Detector common -3.1 VDDUC EQU -3.2 ; Negative unit cell bias -3.5 VDDCL EQU 0.0 ; Column clamp bias VROWOFF EQU -1.0 ; Off bias for rows disabled 0.0 VSSUC EQU -0.5 ; Positive unit cell supply ISLEWREF EQU -4.1 ; Current source -2.0 (-3.0) (use -4.1V for 16.8 uA Iselw - 3/10/03) VDDOUT EQU -0.50 ; Negative bias for OSF driver FET -0.73 VSUB EQU 0.0 ; ROIC subtrate ground ;VSSOUT1 EQU 5.0 ; Positive driver for OSF driver FET ;VSSOUT2 EQU 5.0 ; Positive driver for OSF driver FET ;VSSOUT3 EQU 5.0 ; Positive driver for OSF driver FET ;VSSOUT4 EQU 5.0 ; Positive driver for OSF driver FET VSSOUT1 EQU 2.56 ; Positive driver for OSF driver FET VSSOUT2 EQU 2.56 ; Positive driver for OSF driver FET VSSOUT3 EQU 2.56 ; Positive driver for OSF driver FET VSSOUT4 EQU 2.56 ; Positive driver for OSF driver FET ;VSSOUT1 EQU 6.70 ; Positive driver for OSF driver FET ;VSSOUT2 EQU 6.70 ; Positive driver for OSF driver FET ;VSSOUT3 EQU 6.70 ; Positive driver for OSF driver FET ;VSSOUT4 EQU 6.70 ; Positive driver for OSF driver FET VGREF EQU 0.0 ; Bias for Vref (TBD!!!!!) TSOURCE1 EQU 0.0 ; External current source for Tin1 (should be +1.17 normally) TTLSOURCE EQU 0.0 ; TTL voltage source (should be +5.07 normally) VP EQU 0.0 ; Commoned VPROW annd VNROW VNROW EQU -5.0 ; Negative bias for row shift register -4.9 VGGCL EQU 0.0 ; Column clamp clock VNCOL EQU -3.2 ; Negative bias for column shift register -4.0 ;VREF EQU -0.7 ; VREF (Eddie's 11/19 value at T=293 K) ;VREF EQU 0.16 ; FOR BO MODE ;VREF EQU 0.1 ; FOR BO MODE with N board VREF EQU 0.0 ; FOR NORMAL MODE ;VREF EQU 0.10 ; BJR - grounding test. ;VREF EQU 0.07 ; FOR NORMAL MODE, RQE ;VREF EQU 0.35 ; VREF for T=24 K ; Video offsets ; DAC settings for the video offsets with two coadder boards installed ; Recommend OFFSET not greater than $FD0 and not less than $000 OFFSET EQU $FD0 ; use this for SB-304 MUX (cold) BO MODE ;OFFSET EQU $F00 ; use this for SB-304 MUX (min for 28K) ; OFFSET EQU $9A0 ; use this for SB-304 MUX (needed to get 28-50K all off the bottom rail) NORMAL MODE ;OFFSET EQU $600 ; use this for "N" video board ;OFFSET EQU $0F0 ; use this for SB-304 MUX (warm on bench for air force pattern) ; These constants define the slope and intercept of the DACs in ; output ADU as a function of the above OFFSET ; Appropriate for IDTL coaddder boards at normal operating temp. PP0_0 EQU 32865.699 PP1_0 EQU 32820.581 PP2_0 EQU 32689.120 PP3_0 EQU 32771.884 PP4_0 EQU 32982.305 PP5_0 EQU 32846.121 PP6_0 EQU 32559.233 PP7_0 EQU 32674.982 PP0_1 EQU -16.021943 PP1_1 EQU -16.056462 PP2_1 EQU -16.082675 PP3_1 EQU -15.948860 PP4_1 EQU -16.122941 PP5_1 EQU -16.119988 PP6_1 EQU -16.037983 PP7_1 EQU -16.057203 ; balance all amps to amp 5, assuming the given OFFSET OFFSET0 EQU @CVI((((OFFSET*PP0_1)+PP0_0)-((OFFSET*PP6_1)+PP6_0))/(PP0_1*(-1)))+OFFSET OFFSET1 EQU @CVI((((OFFSET*PP1_1)+PP1_0)-((OFFSET*PP6_1)+PP6_0))/(PP1_1*(-1)))+OFFSET OFFSET2 EQU @CVI((((OFFSET*PP2_1)+PP2_0)-((OFFSET*PP6_1)+PP6_0))/(PP2_1*(-1)))+OFFSET OFFSET3 EQU @CVI((((OFFSET*PP3_1)+PP3_0)-((OFFSET*PP6_1)+PP6_0))/(PP3_1*(-1)))+OFFSET OFFSET4 EQU @CVI((((OFFSET*PP4_1)+PP4_0)-((OFFSET*PP6_1)+PP6_0))/(PP4_1*(-1)))+OFFSET OFFSET5 EQU @CVI((((OFFSET*PP5_1)+PP5_0)-((OFFSET*PP6_1)+PP6_0))/(PP5_1*(-1)))+OFFSET OFFSET6 EQU @CVI((((OFFSET*PP6_1)+PP6_0)-((OFFSET*PP6_1)+PP6_0))/(PP6_1*(-1)))+OFFSET OFFSET7 EQU @CVI((((OFFSET*PP7_1)+PP7_0)-((OFFSET*PP6_1)+PP6_0))/(PP7_1*(-1)))+OFFSET DACS DC END_DACS-DACS-1 ; remember, odd #'s are "0" state (default), and even #'s are "1" state ; These are the DB37 pin IDs CLOCKS DC (CLK2<<8)+(0<<14)+@CVI((CLK_HI_3+MAX_V)/MAX_V2*4095) ; Pin #1 PC1 - Column shift register, phase 1 DC (CLK2<<8)+(1<<14)+@CVI((CLK_LO_2+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(2<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; Pin #2 DC (CLK2<<8)+(3<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(4<<14)+@CVI((CLK_HI_2+MAX_V)/MAX_V2*4095) ; Pin #3 PR1 - Row shift register, phase 1 DC (CLK2<<8)+(5<<14)+@CVI((CLK_LO_2+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(6<<14)+@CVI((CLK_HI_2+MAX_V)/MAX_V2*4095) ; Pin #4 PR2 - Row shift register, phase 2 DC (CLK2<<8)+(7<<14)+@CVI((CLK_LO_2+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(8<<14)+@CVI((CLK_HI_3+MAX_V)/MAX_V2*4095) ; Pin #5 PC2 - Column shift register, phase 2 DC (CLK2<<8)+(9<<14)+@CVI((CLK_LO_2+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(10<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; DC (CLK2<<8)+(11<<14)+@CVI((VGGCL+MAX_V)/MAX_V2*4095) ; Pin #6 VGGCL DC (CLK2<<8)+(12<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; Pin #7 DC (CLK2<<8)+(13<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(14<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; Pin #8 DC (CLK2<<8)+(15<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(16<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; Pin #9 DC (CLK2<<8)+(17<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(18<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; Pin #10 DC (CLK2<<8)+(19<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(20<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; Pin #11 DC (CLK2<<8)+(21<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(22<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; Pin #12 DC (CLK2<<8)+(23<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(24<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; Pin #13 DC (CLK2<<8)+(25<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(26<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; DC (CLK2<<8)+(27<<14)+@CVI((VP+MAX_V)/MAX_V2*4095) ; Pin #14 VP DC (CLK2<<8)+(28<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; DC (CLK2<<8)+(29<<14)+@CVI((VNROW+MAX_V)/MAX_V2*4095) ; Pin #15 VNROW DC (CLK2<<8)+(30<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; Pin #16 DC (CLK2<<8)+(31<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(32<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; Pin #17 DC (CLK2<<8)+(33<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(34<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; DC (CLK2<<8)+(35<<14)+@CVI((TSOURCE1+MAX_V)/MAX_V2*4095) ; Pin #18 TSOURCE1 DC (CLK2<<8)+(36<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; DC (CLK2<<8)+(37<<14)+@CVI((TTLSOURCE+MAX_V)/MAX_V2*4095) ; Pin #19 TTLSOURCE DC (CLK2<<8)+(38<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; Pin #33 DC (CLK2<<8)+(39<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(40<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; DC (CLK2<<8)+(41<<14)+@CVI((VNCOL+MAX_V)/MAX_V2*4095) ; Pin #34 VNCOL DC (CLK2<<8)+(42<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; Pin #35 DC (CLK2<<8)+(43<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(44<<14)+@CVI((CLK_HI_2+MAX_V)/MAX_V2*4095) ; Pin #36 PSCANCOL - Control register scan direction DC (CLK2<<8)+(45<<14)+@CVI((CLK_LO_2+MAX_V)/MAX_V2*4095) DC (CLK2<<8)+(46<<14)+@CVI((CLK_HI_1+MAX_V)/MAX_V2*4095) ; Pin #37 PRST - Row reset clock DC (CLK2<<8)+(47<<14)+@CVI((CLK_LO_1+MAX_V)/MAX_V2*4095) END_CLOCKS ; These are the DB37 pin IDs BIASES DC (CLK4<<8)+(0<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; Pin #1 DC (CLK4<<8)+(1<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(2<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; Pin #2 DC (CLK4<<8)+(3<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(4<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; DC (CLK4<<8)+(5<<14)+@CVI((VDDUC+MAX_V)/MAX_V2*4095) ; Pin #3 VDDUC DC (CLK4<<8)+(6<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; DC (CLK4<<8)+(7<<14)+@CVI((VDETCOM+MAX_V)/MAX_V2*4095) ; Pin #4 VDETCOM DC (CLK4<<8)+(8<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; DC (CLK4<<8)+(9<<14)+@CVI((VDDCL+MAX_V)/MAX_V2*4095) ; Pin #5 VDDCL DC (CLK4<<8)+(10<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; DC (CLK4<<8)+(11<<14)+@CVI((VSSUC+MAX_V)/MAX_V2*4095) ; Pin #6 VSSUC DC (CLK4<<8)+(12<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; DC (CLK4<<8)+(13<<14)+@CVI((VDDOUT+MAX_V)/MAX_V2*4095) ; Pin #7 VDDOUT DC (CLK4<<8)+(14<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; Pin #8 DC (CLK4<<8)+(15<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(16<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; DC (CLK4<<8)+(17<<14)+@CVI((VSUB+MAX_V)/MAX_V2*4095) ; Pin #9 VSUB DC (CLK4<<8)+(18<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; Pin #10 DC (CLK4<<8)+(19<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(20<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; Pin #11 DC (CLK4<<8)+(21<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(22<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; Pin #12 DC (CLK4<<8)+(23<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(24<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; Pin #13 DC (CLK4<<8)+(25<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(26<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; DC (CLK4<<8)+(27<<14)+@CVI((VREF+MAX_V)/MAX_V2*4095) ; Pin #14 VREF DC (CLK4<<8)+(28<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; DC (CLK4<<8)+(29<<14)+@CVI((VSSOUT2+MAX_V)/MAX_V2*4095) ; Pin #15 VSSOUT2 DC (CLK4<<8)+(30<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; DC (CLK4<<8)+(31<<14)+@CVI((VSSOUT4+MAX_V)/MAX_V2*4095) ; Pin #16 VSSOUT4 DC (CLK4<<8)+(32<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; DC (CLK4<<8)+(33<<14)+@CVI((VGREF+MAX_V)/MAX_V2*4095) ; Pin #17 VGREF DC (CLK4<<8)+(34<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; DC (CLK4<<8)+(35<<14)+@CVI((VROWOFF+MAX_V)/MAX_V2*4095) ; Pin #18 VROWOFF DC (CLK4<<8)+(36<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; Pin #19 DC (CLK4<<8)+(37<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(38<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; DC (CLK4<<8)+(39<<14)+@CVI((VSSOUT1+MAX_V)/MAX_V2*4095) ; Pin #33 VSSOUT1 DC (CLK4<<8)+(40<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; DC (CLK4<<8)+(41<<14)+@CVI((VSSOUT3+MAX_V)/MAX_V2*4095) ; Pin #34 VSSOUT3 DC (CLK4<<8)+(42<<14)+@CVI((CLK_HI_1+MAX_V)/MAX_V2*4095) ; Pin #35 VRSTOFF - High clock for row rest FETs (CLOCK) DC (CLK4<<8)+(43<<14)+@CVI((CLK_LO_1+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(44<<14)+@CVI((CLK_HI_4+MAX_V)/MAX_V2*4095) ; Pin #36 VROWON - row FET enable (CLOCK) DC (CLK4<<8)+(45<<14)+@CVI((CLK_LO_4+MAX_V)/MAX_V2*4095) DC (CLK4<<8)+(46<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095) ; DC (CLK4<<8)+(47<<14)+@CVI((ISLEWREF+MAX_V)/MAX_V2*4095) ; Pin #37 ISLEWREF END_BIASES OFFSETS DC $0c0000+OFFSET0 ; Input offset board #0, channel A coadder ; OFFSET0 DC $0c4000+OFFSET1 ; Input offset board #0, channel B coadder ; OFFSET1 DC $0c8000+OFFSET2 ; Input offset board #0, channel C coadder ; OFFSET2 DC $0cc000+OFFSET3 ; Input offset board #0, channel D coadder ; OFFSET3 DC $1c0000+OFFSET4 ; Input offset board #1, channel A coadder ; OFFSET4 DC $1c4000+OFFSET5 ; Input offset board #1, channel B coadder ; OFFSET5 DC $1c8000+OFFSET6 ; Input offset board #1, channel C coadder ; OFFSET6 DC $1cc000+OFFSET7 ; Input offset board #1, channel D coadder ; OFFSET7 END_OFFSETS END_DACS END_WAVEFORMS