; Miscellaneous definitions
VID0	EQU     $000000	; Video board select = 0
VID1	EQU     $001000	; Video board select = 1
CLK2	EQU     $002000 ; Select bottom of clock driver board 
CLK3	EQU     $003000 ; Select top of clock driver board
CLK4	EQU     $004000 ; Select DC bias board
CLK5	EQU     $005000 ; Select DC bias board
AD	EQU	$000001	; Bit to start A/D conversion
XFER	EQU	$000002	; Bit to transfer A/D counts into the A/D FIFO
SXMIT	EQU	$00F060	; Transmit 4 pixels from the first coadder board

; Various delay parameters
VP_DLY  EQU     $2C0000 ; Video delay time for 3 microsec/pixel
VP_DLY_PT EQU	$B80000	; Pass through video delay time for 10.0 microsec/pixel

DLY0	EQU	$000000	; null delay
;DLY1	EQU	$B80000	; LSYNC delay
DLY1	EQU	$9F0000	; LSYNC delay  ; 10us/2 = 1/2 a cycle
DLY2	EQU	$B80000 ; CLK1,2 delay
DLY3	EQU	$FF0000 ; just another delay to play with

; Put all the waveform tables in SRAM
	IF	@SCP("DOWNLOAD","HOST")
	ORG	Y:$100,Y:$100				; Download address
	ELSE
	ORG	Y:$100,P:APL_NUM*N_W_APL+APL_LEN+$340	; ROM address
	ENDIF

; Define switch state bits for CLK2 = "bottom" of clock board and CLK3 = "top" of clock board, 
; and CLK4 = "bottom" of bias board.
VCLK1_2		EQU     1		; Fast clock			(CLK2)
VCLK3_4		EQU     4		; Fast clock			(CLK2)
FSYNC1_2	EQU     $40		; Frame synchronization		(CLK2)
FSYNC3_4	EQU     $80		; Frame synchronization		(CLK2)
READ1_2		EQU     $100		; Pixel read clock		(CLK2)
READ3_4		EQU     $400		; Pixel read clock		(CLK2)
RESET1_2	EQU     1		; Pixel reset clock	(CLK3)
RESET3_4	EQU     4		; Pixel reset clock	(CLK3)
CLK1_1_2	EQU     $100		; Line clocks		(CLK3)
CLK1_3_4	EQU     $200		; Line clocks		(CLK3)
LSYNC1_2	EQU     $400		; Line synchronization	(CLK3)
LSYNC3_4	EQU     $800		; Line synchronization	(CLK3)


; set default pixel sample time (This should usually match DLY1 in waveforms.asm)
PIX_TIM DC      DLY1 ; pixel clock time, written by host computer (10us default here)


; Copy of the clocking bit definition for easy reference. Note only one pixel clock now.
;     DC    CLK2+DLY1+VCLK1_2+VCLK3_4+FSYNC1_2+FSYNC3_4+READ1_2+READ3_4 (new - line1)
;     DC    CLK3+DLY1+RESET1_2+RESET3_4+CLK1_1_2+CLK1_3_4+LSYNC1_2+LSYNC3_4 (new - line2)

;     DC    CLK2+DLY1+FSYNC+LSYNC+VCLK+LCLK1+RESET+READ (old)

WAVE_START
      DC    WAVE_END-WAVE_START-2		; Total number of waves in the table

; use this to stuff a dummy pix into the A2D fifo without clocking the array. 
; this is for speed, as there is no pix clock delay. Use this only if reading less than the
; 2 pix fifo delay (i.e. a 1x1 pix subarray)
STUFF_THE_A2D
	DC	END_STUFF_THE_A2D-STUFF_THE_A2D-2
	DC	VID0+$100000+AD			; Delay needed for the 
	DC	VID0				;   coadder to get started
	DC	VID0
END_STUFF_THE_A2D

FRAME_INIT
      DC    READ_ON-FRAME_INIT-2
      DC    CLK2+DLY1+0000000+0000000+FSYNC1_2+FSYNC3_4+0000000+0000000		; INITAL CLOCK SET
      DC    CLK3+DLY1+00000000+00000000+00000000+00000000+LSYNC1_2+LSYNC3_4	;
      DC    CLK2+DLY1+0000000+0000000+00000000+00000000+0000000+0000000 	; PULSE FSYNC LOW
      DC    CLK2+DLY1+0000000+0000000+FSYNC1_2+FSYNC3_4+0000000+0000000  	; FSYNC HI

READ_ON
      DC    READ_OFF-READ_ON-2
      DC    CLK2+DLY0+0000000+0000000+FSYNC1_2+FSYNC3_4+READ1_2+READ3_4 	; SET READ HI
      DC    CLK3+DLY1+00000000+00000000+CLK1_1_2+CLK1_3_4+LSYNC1_2+LSYNC3_4 ; CLK1* HI, CLK2* LO  - added this

READ_OFF
      DC    VSOURCE_ON-READ_OFF-2
      DC    CLK2+DLY0+0000000+0000000+FSYNC1_2+FSYNC3_4+0000000+0000000 	; SET READ LOW
      DC    CLK3+DLY1+00000000+00000000+00000000+00000000+LSYNC1_2+LSYNC3_4 ; CLK1* LO, CLK2* HI  - added this

VSOURCE_ON  
      DC    VSOURCE_OFF-VSOURCE_ON-1
      DC    CLK4+$000						; SET VSOURCE1_2,3_4 HI
      DC    CLK4+$000						; SET DRAIN1_2,3_4 to 0

VSOURCE_OFF 
      DC    CLOCK_ROW-VSOURCE_OFF-2
      DC    CLK4+$000						; SET VSOURCE1_2,3_4 HI
      DC    CLK4+$050						; SET DRAIN1_2,3_4 to 5.0
;      DC    CLK4+$0A0					        ; SET VSOURCE1_2,3_4 LO

;VSOURCE_ON  
;      DC    VSOURCE_OFF-VSOURCE_ON-2
;      DC    CLK5+$000						; BIASGATE
;      DC    CLK4+$000						; SET VSOURCE1_2,3_4 HI
;;      DC    CLK5+$000						; BIASPOWER
;
;VSOURCE_OFF 
;      DC    CLOCK_ROW-VSOURCE_OFF-2
;;      DC    CLK4+$000					        ; SET VSOURCE1_2,3_4 LO
;      DC    CLK4+$0A0					        ; SET VSOURCE1_2,3_4 LO
;      DC    CLK5+$500						; BIASGATE
;;      DC    CLK5+$005						; BIASPOWER
;
 
CLOCK_VCLK
      DC    CLOCK_ROW-CLOCK_VCLK-2
      DC    CLK2+DLY1+VCLK1_2+VCLK3_4+FSYNC1_2+FSYNC3_4+0000000+0000000 	; PULSE VCLK HI    - simultaneous with LSYNC to save a pulse
      DC    CLK2+DLY1+0000000+0000000+FSYNC1_2+FSYNC3_4+0000000+0000000		; VCLK LOW


CLOCK_ROW
      DC    CLOCK_ROW_RESET-CLOCK_ROW-2
      DC    CLK3+DLY0+00000000+00000000+00000000+00000000+00000000+00000000	; PULSE LSYNC LOW  - simultaneous with VCLK to save a pulse
      DC    CLK2+DLY1+VCLK1_2+VCLK3_4+FSYNC1_2+FSYNC3_4+0000000+0000000 	; PULSE VCLK HI    - simultaneous with LSYNC to save a pulse
      DC    CLK3+DLY0+00000000+00000000+00000000+00000000+LSYNC1_2+LSYNC3_4     ; LSYNC HI
      DC    CLK2+DLY1+0000000+0000000+FSYNC1_2+FSYNC3_4+0000000+0000000		; VCLK LOW

CLOCK_ROW_RESET
      DC    CLOCK_COL_AND_READ_NO_XFER-CLOCK_ROW_RESET-2
      DC    CLK3+DLY0+00000000+00000000+00000000+00000000+00000000+00000000	; PULSE LSYNC LOW  - simultaneous with VCLK to save a pulse
      DC    CLK2+DLY1+VCLK1_2+VCLK3_4+FSYNC1_2+FSYNC3_4+0000000+0000000 	; PULSE VCLK HI    - simultaneous with LSYNC to save a pulse
      DC    CLK3+DLY0+00000000+00000000+00000000+00000000+LSYNC1_2+LSYNC3_4     ; LSYNC HI
      DC    CLK2+DLY1+0000000+0000000+FSYNC1_2+FSYNC3_4+0000000+0000000		; VCLK LOW
      DC    CLK3+DLY1+RESET1_2+RESET3_4+00000000+00000000+LSYNC1_2+LSYNC3_4	; PULSE RESET HI
      DC    CLK3+DLY1+00000000+00000000+00000000+00000000+LSYNC1_2+LSYNC3_4	; RESET LOW


; The first waveform table here does A/D conversion without writing
;   The A/D values to the latch with XFER. The second waveform table does
;   the A/D conversion and writes the previous A/D value to the latch
;   because of the pipeline delay in the ADS937 A/D converter. Each of these
;   should be executed twice by tim.asm, as the pipeline delay is 2 pix. 
CLOCK_COL_AND_READ_NO_XFER
	DC	END_CLOCK_COL_AND_READ_NO_XFER-CLOCK_COL_AND_READ_NO_XFER-2
	DC	CLK3+DLY1+00000000+00000000+00000000+00000000+LSYNC1_2+LSYNC3_4 ; CLK1* LO, CLK2* HI
	DC	CLK3+DLY1+00000000+00000000+CLK1_1_2+CLK1_3_4+LSYNC1_2+LSYNC3_4 ; CLK1* HI, CLK2* LO
	DC	VID0+VP_DLY+AD
	DC	VID0
END_CLOCK_COL_AND_READ_NO_XFER

CLOCK_COL_AND_READ
	DC	END_CLOCK_COL_AND_READ-CLOCK_COL_AND_READ-2
	DC	CLK3+DLY1+00000000+00000000+00000000+00000000+LSYNC1_2+LSYNC3_4 ; CLK1* LO, CLK2* HI
	DC	CLK3+DLY1+00000000+00000000+CLK1_1_2+CLK1_3_4+LSYNC1_2+LSYNC3_4 ; CLK1* HI, CLK2* LO
	DC	VID0+VP_DLY+AD+XFER
	DC	VID0
END_CLOCK_COL_AND_READ



; PT => Pass Through mode, wherein the coadder boards pass pixel data as
;   quickly as possible to the timing board for transmission to the host
; same as non-pt, but with a different delay. Do this once per pix.
CLOCK_COL_AND_READ_PT_NO_XFER
	DC	END_CLOCK_COL_AND_READ_PT_NO_XFER-CLOCK_COL_AND_READ_PT_NO_XFER-2
	DC	CLK3+DLY1+00000000+00000000+00000000+00000000+LSYNC1_2+LSYNC3_4 ; CLK1* LO, CLK2* HI
	DC	CLK3+DLY1+00000000+00000000+CLK1_1_2+CLK1_3_4+LSYNC1_2+LSYNC3_4 ; CLK1* HI, CLK2* LO
	DC	VID0+$100000+AD			; Delay needed for the 
	DC	VID0				;   coadder to get started
	DC	VID0
END_CLOCK_COL_AND_READ_PT_NO_XFER

CLOCK_COL_AND_READ_PT
	DC	END_CLOCK_COL_AND_READ_PT-CLOCK_COL_AND_READ_PT-2
	DC	CLK3+DLY1+00000000+00000000+00000000+00000000+LSYNC1_2+LSYNC3_4 ; CLK1* LO, CLK2* HI
	DC	CLK3+DLY1+00000000+00000000+CLK1_1_2+CLK1_3_4+LSYNC1_2+LSYNC3_4 ; CLK1* HI, CLK2* LO
	DC	VID0+$100000+AD+XFER
	DC	VID0
	DC	SXMIT
END_CLOCK_COL_AND_READ_PT



; These two waveforms tables only do A/D conversions and transfers of
;   latched data to the FIFOs. This is executed twice at the end of reading
;   the array to get the two last A/D values left over because of the 
;   pipeline delay. 
READ_LAST_TWO_PIXELS
	DC	END_READ_LAST_TWO_PIXELS-READ_LAST_TWO_PIXELS-2
	DC	VID0+VP_DLY	; simply a delay, plus AD off
	DC	VID0+AD+XFER	; AD on and transfer
	DC	VID0+VP_DLY	; simply a delay?
	DC	VID0+VP_DLY	; simply a delay, plus AD off
END_READ_LAST_TWO_PIXELS

SXMIT_LAST_TWO_PIXELS
	DC	END_SXMIT_LAST_TWO_PIXELS-SXMIT_LAST_TWO_PIXELS-2
	DC	VID0+VP_DLY_PT		; simply a delay, plus AD off
	DC	VID0+$100000+AD+XFER	; AD on and transfer
	DC	VID0			; AD off
	DC	SXMIT			; transmit to host
END_SXMIT_LAST_TWO_PIXELS


; the following are primarily for BO mode and a few other activities

; this is for advancing the pixel clock without an A2D conversion
CLOCK_ONLY
	DC	END_CLOCK_ONLY-CLOCK_ONLY-2
	DC	CLK3+DLY1+00000000+00000000+00000000+00000000+LSYNC1_2+LSYNC3_4 ; CLK1* LO, CLK2* HI
	DC	CLK3+DLY1+00000000+00000000+CLK1_1_2+CLK1_3_4+LSYNC1_2+LSYNC3_4 ; CLK1* HI, CLK2* LO
END_CLOCK_ONLY

; this is for an A2D conversion without advancing the pixel clock (with transfer)
A2D_ONLY
	DC	END_A2D_ONLY-A2D_ONLY-2

;; pulse read to check delay loop
;        DC      CLK2+DLY0+0000000+0000000+FSYNC1_2+FSYNC3_4+0000000+0000000 	; SET READ LOW
;        DC      CLK2+DLY0+0000000+0000000+FSYNC1_2+FSYNC3_4+READ1_2+READ3_4 	; SET READ HI

	DC	VID0+$100000+AD+XFER
	DC	VID0
	DC	SXMIT
END_A2D_ONLY

; this is for an A2D conversion without advancing the pixel clock (NO transfer)
A2D_ONLY_NO_XFER
	DC	END_A2D_ONLY_NO_XFER-A2D_ONLY_NO_XFER-2
	DC	VID0+$100000+AD
	DC	VID0
	DC	VID0
END_A2D_ONLY_NO_XFER

; this just pulses the rest hi and then low again
PULSE_RESET
      DC    END_PULSE_RESET-PULSE_RESET-2
      DC    CLK3+DLY1+RESET1_2+RESET3_4+00000000+00000000+LSYNC1_2+LSYNC3_4     ; PULSE RESET HI
      DC    CLK3+DLY1+00000000+00000000+00000000+00000000+LSYNC1_2+LSYNC3_4     ; RESET LOW
END_PULSE_RESET
WAVE_END





; Values for IR clock and bias boards. Both boards are jumpered for bipolar operation  
MAX_V	 EQU	 7.5		; Maximum voltage from bias driver board
MAX_V2	 EQU	15.0		; 2 x MAX_V
CLK_ZERO EQU	 0.0		; Zero volts for power-on sequence




;  Zero out ALL the DC biases and clocks during the power-on sequence (zero all lines)
ZERO_BIASES
	DC	END_ZERO_BIASES-ZERO_BIASES-1
	;       clock board
	DC	(CLK2<<8)+(0<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(1<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(2<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(3<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(4<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(5<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(6<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(7<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(8<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(9<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(10<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(11<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(12<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(13<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(14<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(15<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(16<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(17<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(18<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(19<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(20<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(21<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(22<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(23<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(24<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(25<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(26<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(27<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(28<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(29<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(30<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(31<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(32<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(33<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(34<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(35<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(36<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(37<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(38<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(39<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(40<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(41<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(42<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(43<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(44<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(45<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(46<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(47<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)

	; bias board
	DC	(CLK4<<8)+(0<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(1<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(2<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(3<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(4<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(5<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(6<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(7<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(8<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(9<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(10<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(11<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(12<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(13<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(14<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(15<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(16<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(17<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(18<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(19<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(20<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(21<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(22<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(23<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(24<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(25<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(26<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(27<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(28<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(29<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(30<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(31<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(32<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(33<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(34<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(35<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(36<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(37<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(38<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(39<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(40<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(41<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(42<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(43<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(44<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(45<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(46<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
	DC	(CLK4<<8)+(47<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)
END_ZERO_BIASES




; Initialize all DACs




; Clocking voltage definitions
; 	set voltages using CLK2 0-47, just as if setting biases on CLK4, but remember that 
; 	switch states for output lines 0-11 are CLK2 and 
; 	switch states for output lines 12-23 are CLK3
; 	Also, set any unused pins to zero here
;CLK_HI	     EQU 	4.0	; High Clock voltage
;CLK_LO 	     EQU	0.5	; Low Clock voltage

CLK_HI	     EQU 	4.5	; High Clock voltage
CLK_LO 	     EQU	0.5	; Low Clock voltage



; Bias voltage definitions
;	The DC bias board is strapped
;	for bipolar outputs to accomodate the +1.0 volt VssOUT required for the video
;	source followers. The rail voltage is MAX_V = 7.5 volts. MAX_V2 = 2 x MAX_V = 15.0
;	Also, set any unused pins to zero here

DSUB         EQU	0.4	; Detector common         (orig = 0.0)
VSOURCE1_2   EQU	5.0	; Power supply            (orig = 5.0)
VSOURCE3_4   EQU	5.0	; Power supply
VDD1_2 	     EQU	5.0	; Digital Power supply      (orig = 4.5)
VDD3_4       EQU	5.0	; Digital Power supply    (orig = 5.0)
DRAIN1_2     EQU	0.0	; Output amp supply
DRAIN3_4     EQU	0.0	; Output amp supply
DRAIN1_2_OFF     EQU	5.0	; Output amp supply
DRAIN3_4_OFF     EQU	5.0	; Output amp supply
MUXSUB1      EQU	0.01	; Multiplexer ground      (0.01 gives 7.3uV output)
VRESET1_2    EQU	0.1	; Detector reset voltage    (orig = 0.1)
VRESET3_4    EQU	0.1	; Detector reset voltage  (orig = 0.5)
BIASPOWER1_2 EQU	5.0	; Power supply              (orig = 4.5)
BIASPOWER3_4 EQU	5.0	; Power supply            (orig = 5.0)
BIASGATE1_2  EQU	3.5	; Sets SFD current          (orig = 4.0)
BIASGATE3_4  EQU	3.5	; Sets SFD current	(3.0)
BIASGATE1_2_OFF  EQU	0.0	; Sets SFD current	    (orig = 4.0)
BIASGATE3_4_OFF  EQU	0.0	; Sets SFD current
VREFERENCE   EQU	3.5	; Sets VREFERENCE     (4.0)


;DSUB         EQU	0.4	; Detector common         (orig = 0.0)
;VSOURCE1_2   EQU	5.0	; Power supply            (orig = 5.0)
;VSOURCE3_4   EQU	5.0	; Power supply
;VDD1_2       EQU	4.9	; Digital Power supply    (orig = 5.0)
;VDD3_4       EQU	4.9	; Digital Power supply    (orig = 5.0)
;DRAIN1_2     EQU	0.0	; Output amp supply
;DRAIN3_4     EQU	0.0	; Output amp supply
;MUXSUB1      EQU	0.01	; Multiplexer ground      (0.01 gives 7.3uV output)
;VRESET1_2    EQU	0.1	; Detector reset voltage  (orig = 0.5)
;VRESET3_4    EQU	0.1	; Detector reset voltage  (orig = 0.5)
;BIASPOWER1_2 EQU	4.9	; Power supply            (orig = 5.0)
;BIASPOWER3_4 EQU	4.9	; Power supply            (orig = 5.0)
;BIASGATE1_2  EQU	3.4	; Sets SFD current
;BIASGATE3_4  EQU	3.4	; Sets SFD current
;VREFERENCE   EQU	4.0	; Sets VREFERENCE
 


; Video offsets
; 	DAC settings for the video offsets with two coadder boards installed
; 	Recommend OFFSET not greater than $FD0 and not less than $000

;OFFSET  EQU     $F00
;OFFSET  EQU     $7FF	; use this for H1R MUX (jumpered vid board)
OFFSET  EQU     $FC0	; use this for H1R MUX (jumpered vid board)
;OFFSET  EQU     $FD0	; use this for no det, harnesses, jumpered vid board

	; These constants define the slope and intercept of the DACs in
	; output ADU as a function of the above OFFSET
	; Appropriate for IDTL coaddder boards at normal operating temp.

PP0_0   EQU     32865.699
PP1_0   EQU     32820.581
PP2_0   EQU     32689.120
PP3_0   EQU     32771.884
PP4_0   EQU     32982.305
PP5_0   EQU     32846.121
PP6_0   EQU     32559.233
PP7_0   EQU     32674.982

PP0_1   EQU     -16.021943
PP1_1   EQU     -16.056462
PP2_1   EQU     -16.082675
PP3_1   EQU     -15.948860
PP4_1   EQU     -16.122941
PP5_1   EQU     -16.119988
PP6_1   EQU     -16.037983
PP7_1   EQU     -16.057203

	; balance all amps to amp 5, assuming the given OFFSET
OFFSET0 EQU     @CVI((((OFFSET*PP0_1)+PP0_0)-((OFFSET*PP6_1)+PP6_0))/(PP0_1*(-1)))+OFFSET
OFFSET1 EQU     @CVI((((OFFSET*PP1_1)+PP1_0)-((OFFSET*PP6_1)+PP6_0))/(PP1_1*(-1)))+OFFSET
OFFSET2 EQU     @CVI((((OFFSET*PP2_1)+PP2_0)-((OFFSET*PP6_1)+PP6_0))/(PP2_1*(-1)))+OFFSET
OFFSET3 EQU     @CVI((((OFFSET*PP3_1)+PP3_0)-((OFFSET*PP6_1)+PP6_0))/(PP3_1*(-1)))+OFFSET
OFFSET4 EQU     @CVI((((OFFSET*PP4_1)+PP4_0)-((OFFSET*PP6_1)+PP6_0))/(PP4_1*(-1)))+OFFSET
OFFSET5 EQU     @CVI((((OFFSET*PP5_1)+PP5_0)-((OFFSET*PP6_1)+PP6_0))/(PP5_1*(-1)))+OFFSET
OFFSET6 EQU     @CVI((((OFFSET*PP6_1)+PP6_0)-((OFFSET*PP6_1)+PP6_0))/(PP6_1*(-1)))+OFFSET
OFFSET7 EQU     @CVI((((OFFSET*PP7_1)+PP7_0)-((OFFSET*PP6_1)+PP6_0))/(PP7_1*(-1)))+OFFSET



DACS	DC	END_DACS-DACS-1

								; These are the DB37 pin IDs
CLOCKS
        DC      (CLK2<<8)+(0<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #1  VCLK1_2
        DC      (CLK2<<8)+(1<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(2<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)	; Pin #2
	DC	(CLK2<<8)+(3<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)	
        DC      (CLK2<<8)+(4<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #3  VCLK3_4
        DC      (CLK2<<8)+(5<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(6<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)	; Pin #4
	DC	(CLK2<<8)+(7<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)	
	DC	(CLK2<<8)+(8<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)	; Pin #5
	DC	(CLK2<<8)+(9<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)	
	DC	(CLK2<<8)+(10<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)	; Pin #6
	DC	(CLK2<<8)+(11<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)	
        DC      (CLK2<<8)+(12<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #7  FSYNC1_2
        DC      (CLK2<<8)+(13<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)
        DC      (CLK2<<8)+(14<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #8  FSYNC3_4
        DC      (CLK2<<8)+(15<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)
        DC      (CLK2<<8)+(16<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #9  READ1_2
        DC      (CLK2<<8)+(17<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(18<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)	; Pin #10
	DC	(CLK2<<8)+(19<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)	
        DC      (CLK2<<8)+(20<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #11 READ3_4
        DC      (CLK2<<8)+(21<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(22<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)	; Pin #12
	DC	(CLK2<<8)+(23<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)	
        DC      (CLK2<<8)+(24<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #13 RESET1_2
        DC      (CLK2<<8)+(25<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(26<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)	; Pin #14
	DC	(CLK2<<8)+(27<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)	
        DC      (CLK2<<8)+(28<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #15 RESET3_4
        DC      (CLK2<<8)+(29<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(30<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)	; Pin #16
	DC	(CLK2<<8)+(31<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)	
	DC	(CLK2<<8)+(32<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)	; Pin #17
	DC	(CLK2<<8)+(33<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)	
	DC	(CLK2<<8)+(34<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)	
	DC	(CLK2<<8)+(35<<14)+@CVI((VDD3_4+MAX_V)/MAX_V2*4095)	; Pin #18 (BIAS) VDD3_4
	DC	(CLK2<<8)+(36<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)	; Pin #19
	DC	(CLK2<<8)+(37<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)	
	DC	(CLK2<<8)+(38<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)	
	DC	(CLK2<<8)+(39<<14)+@CVI((VDD1_2+MAX_V)/MAX_V2*4095)	; Pin #33 (BIAS) VDD1_2
        DC      (CLK2<<8)+(40<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #34 CLK1_1_2
        DC      (CLK2<<8)+(41<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)
        DC      (CLK2<<8)+(42<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #35 CLK1_3_4
        DC      (CLK2<<8)+(43<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)
        DC      (CLK2<<8)+(44<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #36 LSYNC1_2
        DC      (CLK2<<8)+(45<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)
        DC      (CLK2<<8)+(46<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #37 LSYNC3_4
        DC      (CLK2<<8)+(47<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)
END_CLOCKS

								; These are the DB37 pin IDs
BIASES
	DC	(CLK4<<8)+(0<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		;
	DC	(CLK4<<8)+(1<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; Pin #1
	DC	(CLK4<<8)+(2<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		;
	DC	(CLK4<<8)+(3<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; Pin #2
	DC	(CLK4<<8)+(4<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		;
	DC	(CLK4<<8)+(5<<14)+@CVI((DSUB+MAX_V)/MAX_V2*4095)		; Pin #3  DSUB
	DC	(CLK4<<8)+(6<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; 
	DC	(CLK4<<8)+(7<<14)+@CVI((VREFERENCE+MAX_V)/MAX_V2*4095)		; Pin #4  VREFERENCE
	DC	(CLK4<<8)+(8<<14)+@CVI((DRAIN1_2_OFF+MAX_V)/MAX_V2*4095)		; 
	DC	(CLK4<<8)+(9<<14)+@CVI((DRAIN1_2+MAX_V)/MAX_V2*4095)		; Pin #5  DRAIN1_2
	DC	(CLK4<<8)+(10<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; 
	DC	(CLK4<<8)+(11<<14)+@CVI((VSOURCE1_2+MAX_V)/MAX_V2*4095)		; Pin #6  VSOURCE1_2
	DC	(CLK4<<8)+(12<<14)+@CVI((DRAIN3_4_OFF+MAX_V)/MAX_V2*4095)		; 
	DC	(CLK4<<8)+(13<<14)+@CVI((DRAIN3_4+MAX_V)/MAX_V2*4095)		; Pin #7  DRAIN3_4
	DC	(CLK4<<8)+(14<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; 
	DC	(CLK4<<8)+(15<<14)+@CVI((VSOURCE3_4+MAX_V)/MAX_V2*4095)		; Pin #8  VSOURCE3_4
	DC	(CLK4<<8)+(16<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; 
	DC	(CLK4<<8)+(17<<14)+@CVI((MUXSUB1+MAX_V)/MAX_V2*4095)		; Pin #9  MUXSUB1
	DC	(CLK4<<8)+(18<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; 
	DC	(CLK4<<8)+(19<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; Pin #10
	DC	(CLK4<<8)+(20<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; 
	DC	(CLK4<<8)+(21<<14)+@CVI((VRESET1_2+MAX_V)/MAX_V2*4095)		; Pin #11 VRESET1_2
	DC	(CLK4<<8)+(22<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; 
	DC	(CLK4<<8)+(23<<14)+@CVI((VRESET3_4+MAX_V)/MAX_V2*4095)		; Pin #12 VRESET3_4
	DC	(CLK4<<8)+(24<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; 
	DC	(CLK4<<8)+(25<<14)+@CVI((BIASPOWER1_2+MAX_V)/MAX_V2*4095)	; Pin #13 BIASPOWER1_2
	DC	(CLK4<<8)+(26<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; 
	DC	(CLK4<<8)+(27<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; Pin #14
	DC	(CLK4<<8)+(28<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; 
	DC	(CLK4<<8)+(29<<14)+@CVI((BIASPOWER3_4+MAX_V)/MAX_V2*4095)	; Pin #15 BIASPOWER3_4
	DC	(CLK4<<8)+(30<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; 
	DC	(CLK4<<8)+(31<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; Pin #16
	DC	(CLK4<<8)+(32<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; 
	DC	(CLK4<<8)+(33<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; Pin #17
	DC	(CLK4<<8)+(34<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; 
	DC	(CLK4<<8)+(35<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; Pin #18
	DC	(CLK4<<8)+(36<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; 
	DC	(CLK4<<8)+(37<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; Pin #19
	DC	(CLK4<<8)+(38<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; 
	DC	(CLK4<<8)+(39<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; Pin #33
	DC	(CLK4<<8)+(40<<14)+@CVI((BIASGATE1_2_OFF+MAX_V)/MAX_V2*4095)		;
	DC	(CLK4<<8)+(41<<14)+@CVI((BIASGATE1_2+MAX_V)/MAX_V2*4095)	; Pin #34 BIASGATE1_2
	DC	(CLK4<<8)+(42<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; 
	DC	(CLK4<<8)+(43<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; Pin #35
	DC	(CLK4<<8)+(44<<14)+@CVI((BIASGATE3_4_OFF+MAX_V)/MAX_V2*4095)		; 
	DC	(CLK4<<8)+(45<<14)+@CVI((BIASGATE3_4+MAX_V)/MAX_V2*4095)	; Pin #36 BIASGATE3_4
	DC	(CLK4<<8)+(46<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; 
	DC	(CLK4<<8)+(47<<14)+@CVI((CLK_ZERO+MAX_V)/MAX_V2*4095)		; Pin #37
END_BIASES

OFFSETS
	DC    $0c0000+OFFSET0   ; Input offset board #0, channel A coadder	; OFFSET0
	DC    $0c4000+OFFSET1   ; Input offset board #0, channel B coadder	; OFFSET1
	DC    $0c8000+OFFSET2   ; Input offset board #0, channel C coadder	; OFFSET2
	DC    $0cc000+OFFSET3   ; Input offset board #0, channel D coadder	; OFFSET3
	DC    $1c0000+OFFSET4   ; Input offset board #1, channel A coadder	; OFFSET4
	DC    $1c4000+OFFSET5   ; Input offset board #1, channel B coadder	; OFFSET5
	DC    $1c8000+OFFSET6   ; Input offset board #1, channel C coadder	; OFFSET6
	DC    $1cc000+OFFSET7   ; Input offset board #1, channel D coadder	; OFFSET7
END_OFFSETS

END_DACS


END_WAVEFORMS