COMMENT * This file is used to generate DSP code for the second generation timing boards to operate one 512 x 512 pixel quadrant of a HAWAII-1R array with two coadder boards. * PAGE 132 ; Printronix page width - 132 columns ; Define a section name so it doesn't conflict with other application programs SECTION TIM_HAWAII_1R ; Include a header file that defines global parameters INCLUDE "../DSPlib/timhdr.asm" APL_NUM EQU 0 ; Application number from 0 to 3 CC EQU TIMREV4+NGST+COADDER SCR EQU $FFF0 ; SCI Control Register SSR EQU $FFF1 ; SCI Status Register SCCR EQU $FFF2 ; SCI Clock Control Register WRSCI EQU $FFF4 ; Write least significant byte to SCI port WRSCI0 EQU $FFF4 ; Write least significant byte to SCI port WRSCI1 EQU $FFF5 ; Write middle significant byte to SCI port WRSCI2 EQU $FFF6 ; Write most significant byte to SCI port SRAM_AD EQU $5F0 ; Address in timing board SRAM where coadder code is P_COADD EQU $E001 ; Start of coadder code in EEPROM RST_CA EQU 3 ; Timing board resets coadder board (Rev 4B, which IDTL has) ; NOTE error in docs! should be 4B=3 3B=5 ; Software status bit definitions for the program only RST_MODE EQU 16 ; 0 for global reset, 1 for row-by-row reset CDS_MODE EQU 17 ; 0 for single sampling, 1 for CDS PTR_MODE EQU 18 ; 0 for Coadder arithmetic, 1 for pass through mode UTR_MODE EQU 19 ; 0 for normal, 1 up-the-ramp readout BO_MODE EQU 20 ; 0 for normal, 1 Bright Object ;****************************************************************************** ;**** CLOCKING CODE IN SRAM PROGRAM SPACE **** ;****************************************************************************** ; Specify execution and load addresses IF @SCP("DOWNLOAD","HOST") ORG P:APL_ADR,P:APL_ADR ; Download address ELSE ORG P:APL_ADR,P:APL_NUM*N_W_APL ; EEPROM address ENDIF ;****************************************************************************** ; Normal readout of array with global reset RD_ARRAY ; first, calculate some numbers MOVE Y:=$2F0 WARN 'Application P: program is too large!' ; Make sure program ENDIF ; will not overflow ;****************************************************************************** ; **************** PROGRAM CODE IN SRAM PROGRAM SPACE ******************* ;****************************************************************************** ; Put all the following code in SRAM, starting at P:$2F0. IF @SCP("DOWNLOAD","HOST") ORG P:$2F0,P:$2F0 ; Download address ELSE ORG P:$2F0,P:APL_NUM*N_W_APL+APL_LEN ; ROM address ENDIF ;****************************************************************************** ; this is just for testing purposes. CALC_EXP_TIME ; exptime logic moved here from ExposureCommand.java since it will ; be device specific. ; here is the formula for a single readout time in 0.1 millis: ; rows and cols are for a single quad, so 512x512 for full array. ; (a1*(rows-1))+(a2*(cols+1)*rows) ; a1=226 ; a2=119 ; MOVE X:8,A ; Not-CDS value = (512 x 512) / 8 (loop 8 times) JCLR #CDS_MODE,X:STATUS,XMIT MOVE #>16,A ; CDS value = 2 x (512 x 512) / 8 (loop 16 times) XMIT DO A,L_XTIM1 ; 32-bits per pixel MOVE #$1000,X0 ; For two coadder boards transmit (loop 4096 times) DO X0,L_TXIM2 ; eight pixels per loop MOVE #$00F060,A ; Write SXMIT out MOVE A,X:(R6) ; send 4 16-bit pix, board 1 MOVE #XMT_DLY,X0 ; Delay for pixel transmission MOVE X0,X:(R6) MOVE #$00F060,A MOVE A,X:(R6) ; send 4 16-bit pix, board 1 MOVE #XMT_DLY,X0 MOVE X0,X:(R6) MOVE #$00F0E4,A MOVE A,X:(R6) ; send 4 16-bit pix, board 2 MOVE #XMT_DLY,X0 MOVE X0,X:(R6) MOVE #$00F0E4,A MOVE A,X:(R6) ; send 4 16-bit pix, board 2 MOVE #XMT_DLY,X0 MOVE X0,X:(R6) L_TXIM2 NOP L_XTIM1 JSR 24,X0 ; Check for argument less than 32 CMP X0,A JGE ERR_SM1 MOVE A,B MOVE #>7,X0 AND X0,B MOVE #>$18,X0 AND X0,A JNE $08,X0 CMP X0,A ; Test for 8 <= MUX number <= 15 JNE $10,X0 CMP X0,A ; Test for 16 <= MUX number <= 23 JNE 24,X0 ; Check for argument less than 32 CMP X0,A JGE ERR_SM2 REP #6 LSL A MOVE A,B MOVE #$1C0,X0 AND X0,B MOVE #>$600,X0 AND X0,A JNE $200,X0 CMP X0,A ; Test for 8 <= MUX number <= 15 JNE $400,X0 CMP X0,A ; Test for 16 <= MUX number <= 23 JNE Power reset BSET #PWRST,X:PBD ; PWRST = 1 => Power reset BSET #HVEN,X:PBD MOVE #TST_RCV,X0 MOVE X0,X: Power reset BSET #PWRST,X:PBD ; PWRST = 1 => Power reset BSET #HVEN,X:PBD ; Now ramp up the low voltages (+/- 6.5V, 16.5V) BCLR #LVEN,X:PBD ; LVEN = Low => Turn on +/- 6.5V, BCLR #PWRST,X:PBD ; +/- 16.5V MOVE X: