; ********************** START OF COADDER PROGRAM *********************** ; Define a section name so it doesn't conflict with other application programs SECTION COADD ; Define some useful DSP register locations RST_ISR EQU $0 ; Hardware reset interrupt BUF_STR EQU $80 ; Starting address of buffers in X: BUF_LEN EQU $20 ; Length of buffers COM_BUF EQU BUF_STR ; Starting address of command buffer in X: COM_TBL EQU COM_BUF+BUF_LEN ; Starting address of command table in X: ADR_TBL EQU COM_TBL+BUF_LEN ; Table with SRAM addresses for pixels APL_ADR EQU $10 ; Start of application code, $10 for now APL_LEN EQU $2F0-APL_ADR ; Length of application code area ROM_OFF EQU $4AAB ; Offset address into timing board ROM ; so it gets placed at $6001 = 24k into ; 32k ROM SRAM_AD EQU $5F0 ; Address in timing board SRAM where coadder code is X_TABLE EQU 0 ; Starting address of X: memory table ; DSP specific addresses BCR EQU $FFFE ; Bus (=Port A) Control Register -> Wait States PCC EQU $FFE1 ; Port C Control Register PCDDR EQU $FFE3 ; Port C Data Direction Register PCD EQU $FFE5 ; Port C Data Register CRA EQU $FFEC ; SSI Control Register A CRB EQU $FFED ; SSI Control Register B SSISR EQU $FFEE ; SSI Status Register SSIRX EQU $FFEF ; SSI Receiver SSITX EQU $FFEF ; SSI Transmitter PBC EQU $FFE0 ; Port B Control Register PBDDR EQU $FFE2 ; Port B Data Direction Register PBD EQU $FFE4 ; Port B Data Register PCTL EQU $FFFD ; PLL control register IPR EQU $FFFF ; Interrupt Priority Register SCR EQU $FFF0 SSR EQU $FFF1 SCCR EQU $FFF2 STXL EQU $FFF4 SRXL EQU $FFF4 SSI_TDE EQU 6 ; SSI Transmitter data register empty SSI_RDF EQU 7 ; SSI Receiver data register full RCV_ERR EQU 2 ; Place in X: memory for SSI errors ; Board addresses RDFIFO EQU $C000 ; Read A/D FIFO into DSP WRCAFIFO EQU $C001 ; Write from DSP to coadder FIFO RSTFIFO EQU $C002 ; Reset both A/D and coadder FIFOs RSTSRAM EQU $8000 ; Start 32-bit mode pointer with D0-D23 (X: memory) ; Parallel port bit numbers, Port B SRAMADDR16 EQU 4 ; SRAM address line 16 SRAMADDR17 EQU 5 ; SRAM address line 17 SRAMADDR18 EQU 6 ; SRAM address line 18 SRAMADDR19 EQU 7 ; SRAM address line 19 GAIN EQU 8 ; A/D gain EF EQU 9 ; Bit number of incomimng FIFO empty flag HF EQU 10 ; Bit number of incoming FIFO half full flag ; Define a little table for X: memory entries NCOADDS EQU X_TABLE NUTR EQU NCOADDS+1 CDS EQU NUTR+1 NFS EQU CDS+1 NCOLS EQU NFS+1 NROWS EQU NCOLS+1 NREADS EQU NROWS+1 ; More flags, Port C M24_32 EQU 2 ; 24- or 32-bit coaddition, Port C CAHF EQU 5 ; Cadder FIFO half full flag, on Port C MEM_ERR EQU 3 ; Set if memory testing error ;************************************************************************** ; * ; Permanent address register assignments * ; R1 - Pointer to commands received pending processing * ; R2 - Pointer to processed commands * ; R3 - Pixel address of frame being coadded * ; R4 - Pixel address of frame being transmitted * ; R5 - RDFIFO address = $C000 * ; R6 - WRCAFIFO address = $C001 * ; * ;************************************************************************** ;****************************************************************************** ;**** COADDER CODE IN SRAM PROGRAM SPACE **** ;****************************************************************************** ; Specify the load address for the coadder code IF @SCP("DOWNLOAD","HOST") ORG P:RST_ISR,P:$5F0 ; Download address ELSE ORG P:RST_ISR,P:RST_ISR+ROM_OFF ; ROM address ENDIF ; Special address for two words for downloading over coadder SCI port DC END_ADR ; Number of boot code words DC $0 ; Starting address of boot code ; After RESET jump to initialization code IF @SCP("DOWNLOAD","HOST") ORG P:RST_ISR,P:$5F0+2 ; Download address ELSE ORG P:RST_ISR,P:RST_ISR+ROM_OFF+2 ; ROM address ENDIF JMP 32,X1 ; Correct for the circular buffer ADD X1,A L_C32 CMP Y0,A ; Has it been incremented to RCV_BUF + NWORDS? JLT Yes correlated double JSR $6FF WARN 'Internal P: memory overflow!' ENDIF ENDSEC ; End of section COADD