COMMENT *

This file is used to generate DSP code for the TIMII second generation 
    timing board. This is Rev. 3.00 software.     

Timing modified for Datel A/D converter starting 11-6-96
Modified for timing board Rev. 4B Feb. 17, 1997
Put rarely used and non-time critical routines in SRAM program memory 
	(P: > $200)

-d DOWNLOAD 1	To generate code for downloading to DSP memory.
-d DOWNLOAD 0	To generate code for writing to the EEPROM.

	*
	PAGE    132     ; Printronix page width - 132 columns

; Define a section name so it doesn't conflict with other application programs
	SECTION	TIMTEST

; These are also defined in "timboot.asm", so be sure they agree
APL_NUM	EQU	3	; Application number from 0 to 3
APL_ADR	EQU	$110	; P: memory location where application code begins
APL_LEN	EQU	$200-APL_ADR ; Maximum length of application program
COM_TBL EQU     $80     ; Starting address of command table in X: memory
N_W_APL	EQU	$500	; Number of words in each application

; Board status bits, defined at X:<STATUS = X:0
IDLING  EQU     0	; Set if in idle mode => clocking out
IDLMODE	EQU	1	; Set if need to idle after readout
ST_RDC	EQU	4	; Set if executing 'RDC' command - reading out

; Define some timing board addresses
WRLATCH	EQU	$FFC1	; Write to timing board latch
WRFO	EQU	$FFC0	; Write to fiber optic transmitter
RDAD0	EQU	$FFA0	; Address for reading A/D #0
RDAD1	EQU	$FFA1	; Address for reading A/D #1
SSIRX	EQU	$FFEF	; SSI Transmit and Receive data register
SSITX	EQU	$FFEF	; SSI Transmit and Receive data register
SSISR	EQU	$FFEE	; SSI Status Register
PBD	EQU	$FFE4	; Port B Data Register
PCC     EQU     $FFE1   ; Port C Control Register
PCDDR	EQU	$FFE3	; Port C Data Direction Register
PCD     EQU     $FFE5   ; Port C Data Register
BCR     EQU     $FFFE   ; Bus (=Port A) Control Register -> Wait States
RSTWDT	EQU	$6000	; Address to reset the timing board watchdog timer

; CCD clock voltage definitions
VIDEO	EQU	$000000	; Video processor board select = 0
CLK	EQU	$002000	; Clock driver board select = all boards for clocks 
CLK2	EQU	$002000	; Clock driver board select = 2 for DAC setting
CLK3	EQU	$003000	; Clock driver board select = 3 for DAC setting
CLK4	EQU	$004000	; Clock driver board select = 4 for DAC setting
P_DELAY	EQU	$020000	; Parallel clock delay
R_HI	EQU	3000	; Reset and Serial clocks High +4.0 volts
R_LO	EQU	770	; Reset and Serial clocks Low  -6.0 volts
SI_HI	EQU	2710	; Storage and Image High +3.0 volts
SI_LO	EQU	620	; Storage and Image Low  -7.0 volts
WW	EQU	1	; Word width = 1 for 16-bit image data, 0 for 24-bit
CDAC	EQU	0	; Bit number in U25 for clearing DACs
DUALCLK	EQU	1	; Set to clock two halves of clock driver board together
ENCK	EQU	2	; Bit number in U25 for enabling analog switches
FD15	EQU	10	; Forced data bit 15
FMODE	EQU	12	; Forced data bit 15 mode

;SXMIT	EQU     $00F060	; Series transmit A/D channels #0 to #3
;SXMIT	EQU     $00F020	; Series transmit A/D channels #0 to #1
;SXMIT	EQU     $00F000	; Series transmit A/D channel #0 only
;SXMIT  EQU     $00F021	; Series transmit A/D channel #1 only
;SXMIT  EQU     $00F042	; Series transmit A/D channel #2 only
;SXMIT  EQU     $00F063	; Series transmit A/D channel #3 only
;SXMIT  EQU     $00F062	; Series transmit A/D channels #2 to #3
;SXMIT	EQU     $00F0A0	; Series transmit A/D channels #0 to #5
;SXMIT	EQU     $00F0E4	; Series transmit A/D channels #4 to #7
;SXMIT	EQU     $00F0E0	; Series transmit A/D channels #0 to #7
;SXMIT	EQU     $00F0A2	; Series transmit A/D channels #2 to #5

SXMIT	EQU     $00F000

;**************************************************************************
;                   	                                                  *
;    Permanent address register assignments                               *
;	 R1 - Address of SSI receiver contents				  *
;	 R2 - Address of SCI receiver contents				  *
;        R3 - Pointer to current top of command buffer                    *
;        R4 - Pointer to processed contents of command buffer		  *
;        R5 - Temporary register for processing SSI and SCI contents      *
;        R6 - CCD clock driver address for CCD #0 = $FF80                 *
;                It is also the A/D address of analog board #0            *
;                                                                         *
;    Other registers                                                      *
;        R0, R7 - Temporary registers used all over the place.            *
;        R5 - Can be used as a temporary register but is circular,        *
;               modulo 32.       					  *
;**************************************************************************

;  Specify execution and load addresses
	IF	DOWNLOAD
	ORG	P:APL_ADR,P:APL_ADR		; Download address
	ELSE
	ORG     P:APL_ADR,P:APL_NUM*N_W_APL	; EEPROM address
	ENDIF

; Keep the CCD idling when not reading out
IDLE	DO      Y:<NSR,IDL1     ; Loop over number of pixels per line
	MOVE    #<SERIAL_IDLE,R0 ; Serial transfer on pixel
	JSR     <CLOCK  	; Go to it
	JSR	<GET_RCV	; Check for FO or SSI commands
	JCC	<NO_COM		; Continue IDLE if no commands received
	ENDDO   		; Cancel the DO loop system stack numbers
	JMP     <CHK_SSI	; Go process header and command
NO_COM  NOP
IDL1	
	MOVE    #<PARALLEL,R0	; Address of parallel clocking waveform
	JSR     <CLOCK  	; Go clock out the CCD charge
	JMP     <IDLE

;  ***********************   CCD  READOUT   ***********************
; Overall loop - transfer and read NPR lines
;
; Clear out the serial shift register
RDCCD	BSET	#ST_RDC,X:<STATUS ; Set status to reading out
	BSET	#WW,X:PBD		; Set WW = 1 for 16-bit image data

	DO      Y:<NSCLR,LSCLR		; Loop over number of pixels to skip
        MOVE    #<SSKIP,R0      	; Address of serial skipping waveforms
        JSR     <CLOCK          	; Go clock out the CCD charge
        NOP                     	; Do loop restriction
LSCLR  

; Start the loop for parallel shifting desired number of lines
	CLR	A
	MOVE	A,Y:<TST_DAT
	DO      Y:<NPR,LPR      	; Loop over each line readout

; Check to see if a command has been sent. Only the ABORT command is allowed
	JSR	<GET_RCV		; Was a command received?
	JCC	<CONT_RD		; If no, continue reading out
	JMP	<CHK_SSI		; If yes, go process it

; Abort the readout currently underway
ABR_RDC	JCLR	#ST_RDC,X:<STATUS,START	; Do nothing - we're not reading out
	ENDDO				; Properly terminate LPR readout loop
	JMP	<LPR

CONT_RD	DO      Y:<NSR,LSR		; Loop over number of pixels per line
;	MOVE    #<SERIAL_IDLE,R0
;	JSR	<CLOCK

	REP	#20			; #20 => 1.0 microsec per pixel
	NOP

; Increment pixel counts by one
	MOVE	X:<ONE,X1
	MOVE	Y:<TST_DAT,A
	ADD	X1,A
	MOVE	A,Y:<TST_DAT		; Pixel data = Y:TST_DAT = Y:TST_DAT + 1
	MOVEP	A,Y:WRFO		; Transmit it to fiber optic	
LSR					; End of loop for serial register
	NOP				; DO loop restriction
LPR					; End of loop for parallel register

	JSR	<PAL_DLY	; Wait for last fiber optic transmission
	BCLR	#WW,X:PBD	; Clear WW to 0 for 32-bit commands
	BCLR	#ST_RDC,X:<STATUS ; Set status to reading out
	JCLR	#IDLMODE,X:<STATUS,START ; Don't idle after readout
	BSET	#IDLING,X:<STATUS ; Idle after readout
        JMP     <START		; Wait for a new command

; Automated test of on-board SRAM memory
TEST_MEM
	MOVEP	#$0010,X:BCR	; Wait states for external memory accesses
				;   Ext. X:, Ext. Y, Ext. P:, Ext. I/O
				; 1 wait state required for external SRAM access
; Test P: memory
	MOVE	Y:<CFFFFFF,A
	JSR	<CONST_P
	JNE	<TST_ERR
	CLR	A
	JSR	<CONST_P
	JNE	<TST_ERR
	MOVE	Y:<C555555,A
	JSR	<CONST_P
	JNE	<TST_ERR
	MOVE	Y:<CAAAAAA,A
	JSR	<CONST_P
	JNE	<TST_ERR
	JSR	<INCR_P
	JNE	<TST_ERR

; Test X: memory
	MOVE	Y:<CFFFFFF,A
	JSR	<CONST_X
	JNE	<TST_ERR
	CLR	A
	JSR	<CONST_X
	JNE	<TST_ERR
	MOVE	Y:<C555555,A
	JSR	<CONST_X
	JNE	<TST_ERR
	MOVE	Y:<CAAAAAA,A
	JSR	<CONST_X
	JNE	<TST_ERR
	JSR	<INCR_X
	JNE	<TST_ERR

; Test Y: memory
	MOVE	Y:<CFFFFFF,A
	JSR	<CONST_Y
	JNE	<TST_ERR
	CLR	A
	JSR	<CONST_Y
	JNE	<TST_ERR
	MOVE	Y:<C555555,A
	JSR	<CONST_Y
	JNE	<TST_ERR
	MOVE	Y:<CAAAAAA,A
	JSR	<CONST_Y
	JNE	<TST_ERR
	JSR	<INCR_Y
	JNE	<TST_ERR

; No error, so return with 'DON'
ALL_OK	MOVEP	#$0181,X:BCR	; Wait states for external memory accesses
				;   Ext. X:, Ext. Y, Ext. P:, Ext. I/O
	JMP	<FINISH

; There's been an error
TST_ERR	MOVEP	#$0181,X:BCR	; Wait states for external memory accesses
				;   Ext. X:, Ext. Y, Ext. P:, Ext. I/O
	MOVE	X:<ERR,X0
	JMP	<FINISH1

; Test constant numbers written into P: memory
CONST_P	MOVE	Y:<C1A00,X0
	MOVE	Y:<C600,R0	; Don't write over the P: program
	DO	X0,L_WRPC
	MOVE	A,P:(R0)+
L_WRPC
	MOVE	Y:<C600,R0
	DO	X0,L_RDPC
	MOVE	P:(R0)+,X0
	CMP	X0,A
	JEQ	<L_RDPC0
	ENDDO
	JMP	<L_RTSC
L_RDPC0	NOP
L_RDPC
L_RTSC	RTS

; Increment numbers written into P: memory
INCR_P	CLR	A
	MOVE	Y:<C9d7,X0
	MOVE	Y:<C600,R0
	MOVE	Y:<C1A00,Y1
	DO	Y1,L_WRPI
	ADD	X0,A
	MOVE	A1,P:(R0)+
L_WRPI
	CLR	A
	MOVE	Y:<C600,R0
	DO	Y1,L_RDPI
	ADD	X0,A
	MOVE	#0,A2
	JCLR	#23,A1,L_RDPI1
	MOVE	Y:<CFF,A2
L_RDPI1	MOVE	P:(R0)+,Y0
	CMP	Y0,A
	JEQ	<L_RDPI0
	ENDDO
	RTS
L_RDPI0	NOP
L_RDPI	RTS

; Test constant numbers written into X: memory
CONST_X	MOVE	Y:<C1F00,X0
	MOVE	Y:<C100,R0
	DO	X0,L_WRXC
	MOVE	A,X:(R0)+
L_WRXC
	MOVE	Y:<C100,R0
	DO	X0,L_RDXC
	MOVE	X:(R0)+,X0
	CMP	X0,A
	JEQ	<L_RDXC0
	ENDDO
	RTS
L_RDXC0	NOP
L_RDXC	RTS

; Increment numbers written into X: memory
INCR_X	CLR	A
	MOVE	Y:<C841,X0
	MOVE	Y:<C100,R0
	MOVE	Y:<C1F00,Y1
	DO	Y1,L_WRXI
	ADD	X0,A
	MOVE	A1,X:(R0)+
L_WRXI
	CLR	A
	MOVE	Y:<C100,R0
	DO	Y1,L_RDXI
	ADD	X0,A
	MOVE	#0,A2
	JCLR	#23,A1,L_RDXI1
	MOVE	Y:<CFF,A2
L_RDXI1	MOVE	X:(R0)+,Y0
	CMP	Y0,A
	JEQ	<L_RDXI0
	ENDDO
	RTS
L_RDXI0	NOP
L_RDXI	RTS

; Test constant numbers written into Y: memory
CONST_Y	MOVE	Y:<C3F00,X0
	MOVE	Y:<C100,R0
	DO	X0,L_WRYC
	MOVE	A,Y:(R0)+
L_WRYC
	MOVE	Y:<C100,R0
	DO	X0,L_RDYC
	MOVE	Y:(R0)+,X0
	CMP	X0,A
	JEQ	<L_RDYC0
	ENDDO
	RTS
L_RDYC0	NOP
L_RDYC	RTS

; Increment numbers written into Y: memory
INCR_Y	CLR	A
	MOVE	Y:<C40f,X0
	MOVE	Y:<C100,R0
	MOVE	Y:<C3F00,Y1
	DO	Y1,L_WRYI
	ADD	X0,A
	MOVE	A1,Y:(R0)+
L_WRYI
	CLR	A
	MOVE	Y:<C100,R0
	DO	Y1,L_RDYI
	ADD	X0,A
	MOVE	#0,A2
	JCLR	#23,A1,L_RDYI1
	MOVE	Y:<CFF,A2
L_RDYI1	MOVE	Y:(R0)+,Y0
	CMP	Y0,A
	JEQ	<L_RDYI0
	ENDDO
	RTS
L_RDYI0	NOP
L_RDYI	RTS

;  *************************    SUBROUTINES    ***********************
; Delay for serial writes to the PALs and DACs by 8 microsec
PAL_DLY	DO	#250,DLY	 ; Wait 8 usec for serial data transmission
	NOP
	NOP
DLY	NOP
	RTS

;  Update the DACs
SET_DAC	MOVE	Y:(R0)+,X0		; Get the number of table entries
        DO      X0,SET_L0		; Repeat X0 times
        MOVEP	Y:(R0)+,X:SSITX		; Send out the waveform
	JSR	<PAL_DLY		; Wait for SSI and PAL to be empty
	NOP				; Do loop restriction
SET_L0
        RTS                     	; Return from subroutine

; Core subroutine for clocking out CCD charge
CLOCK   MOVE    Y:(R0)+,X0      	; # of waveform entries 
        MOVE    Y:(R0)+,A       	; Start the pipeline
        DO      X0,CLK1                 ; Repeat X0 times
        MOVE    A,X:(R6) Y:(R0)+,A      ; Send out the waveform
CLK1
        MOVE    A,X:(R6)        	; Flush out the pipeline
        RTS                     	; Return from subroutine

; Check for program overflow
        IF	@CVS(N,*)>=$200
        WARN    'Application P: program is too large!'	; Make sure program
	ENDIF						;  will not overflow

;  ****************  PROGRAM CODE IN SRAM PROGRAM SPACE    *******************
; Put all the following code in SRAM, starting at P:$200.
	IF	DOWNLOAD
	ORG	P:$200,P:$200				; Download address
	ELSE
	ORG	P:$200,P:APL_NUM*N_W_APL+APL_LEN	; EEPROM address
	ENDIF

; Set all the DC bias voltages and video processor offset values, reading
;   them from the table labeled DACS in this file
SETBIAS	JSR	<SER_ANA
	BSET	#CDAC,X:<LATCH		; Disable clearing of DACs
	BSET	#DUALCLK,X:<LATCH	; Enable parallel switching of clocks
	BSET	#ENCK,X:<LATCH		; Enable clock and DAC output switches
	MOVEP	X:LATCH,Y:WRLATCH 	; Disable clear of DAC and enable clocks
	JSR	<PAL_DLY		; Delay for all this to happen
	JSR	<PAL_DLY		; Delay for all this to happen

; Read DAC values from a table, and set DACs
	MOVE	#DACS,R0	; Get starting address of DAC values
	JSR	<SET_DAC

; Set all video processor analog switches to open to disable them (1 => OFF)
	MOVE	#$000FFF,A 
	MOVE    A,X:(R6)	; Send out the waveform
	NOP

; Let the DAC voltages all ramp up before exiting
	MOVE	#400,A		; Delay 4 millisec
	DO	A,L_SBV1
	JSR	<PAL_DLY 	; Delay for all this to happen
	NOP
L_SBV1
	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<FINISH

; Enable serial communication to the analog boards
SER_ANA	BSET	#0,X:PBD	; Set H0 for analog boards SSI
	MOVEP	#$0000,X:PCC	; Software reset of SSI
	BCLR	#10,X:CRB	; Change SSI to continuous clock for analog 
	MOVEP   #$0160,X:PCC	; Re-enable the SSI
	RTS

; Enable serial communication to the utility board
SER_UTL	MOVEP	#$0000,X:PCC	; Software reset of SSI
	BSET	#10,X:CRB	; Change SSI to gated clock for utility board 
	MOVEP   #$0160,X:PCC	; Enable the SSI
	BCLR	#0,X:PBD	; Clear H0 for utility board SSI
	RTS

; Abort current exposure; make sure the utility board does not upset things
ABORT	JCLR    #SSI_TDE,X:SSISR,*	; Continue if SSI XMT register is empty
        MOVEP	#$020302,X:SSITX	; Write to SSI buffer
	JCLR    #SSI_TDE,X:SSISR,*	; Continue if SSI XMT register is empty
        MOVEP	#'AEX',X:SSITX		; Write to SSI buffer

	MOVE	#20000,X1		; Throw away whatever the utility board 
	DO	X1,UTIL0		;   sends, but maintain protocol
	JCLR	#SSI_RDF,X:SSISR,UTIL1	; Skip if no utility board word
	MOVEP   X:SSIRX,X1		; Reqd utility board word
	MOVE	X:<UTL_REQ,A		; Is it a utility request?
	CMP	X1,A
	JNE	<UTIL1			; Yes
	JCLR    #SSI_TDE,X:SSISR,*	; Wait for transmitter to be empty
	MOVEP	X:TIM_ACK,X:SSITX	; Write acknowledge to utility board
UTIL1	NOP
UTIL0	JMP	<ABR_RDC

; Set software to IDLE mode
IDL	BSET    #IDLING,X:<STATUS
	JMP     <FINISH		; Need to send header ID and 'DON'

; Come to here on a 'STP' command so 'DON' can be sent
STP     BCLR    #IDLING,X:<STATUS
	JMP     <FINISH

; Fast clear image before each exposure
CLEAR	DO      Y:<NPCLR,LPCLR	; Loop over number of lines in image
	MOVE    #<PARALLEL,R0	; Address of parallel transfer waveform
	JSR     <CLOCK  	; Go clock out the CCD charge
	NOP			; Do loop restriction
LPCLR
	BCLR	#IDLMODE,X:<STATUS
	JCLR	#IDLING,X:<STATUS,FINISH
	BSET	#IDLMODE,X:<STATUS	; Idle after readout
	BCLR    #IDLING,X:<STATUS 	; Don't idle during exposure
	JMP     <FINISH

; Clear all video processor analog switches to lower their power dissipation
CLR_SWS	JSR	<SER_ANA	; Set SSI to analog board communication
	MOVE	#$0C3000,A	; Value of integrate speed and gain switches
	CLR	B
	MOVE	#$100000,X0	; Increment over board numbers for DAC writes
	MOVE	#$001000,X1	; Increment over board numbers for WRSS writes
	DO	#15,L_VIDEO	; Fifteen video processor boards maximum
	MOVEP	A,X:SSITX 	; Gain, integrate speed
	ADD	X0,A
	MOVE	B,X:WRSS
	JSR	<PAL_DLY	; Delay for the serial data transmission
	ADD	X1,B
L_VIDEO	

	BCLR	#CDAC,X:<LATCH		; Enable clearing of DACs
	BCLR	#ENCK,X:<LATCH		; Disable clock and DAC output switches
	MOVEP	X:LATCH,Y:WRLATCH 	; Execute these two operations
	BCLR    #IDLING,X:<STATUS	; Stop all clocking so DACs don't heat
	JSR	<SER_UTL		; Return SSI to utility board
	JMP	<FINISH

; Set the video processor gain and integrator speed for all video boards
;  Command syntax is  SGN  #GAIN  #SPEED, #GAIN = 1, 2, 5 or 10	
;					  #SPEED = 0 for slow, 1 for fast
ST_GAIN	JSR	<SER_ANA	; Set SSI to analog board communication
	MOVE	X:(R4)+,A	; Gain value (1,2,5 or 10)
	MOVE	#>1,X0
	CMP	X0,A		; Check for gain = x1
	JNE	<STG2
	MOVE	#>$77,B
	JMP	<STG_A
STG2	MOVE	#>2,X0		; Check for gain = x2
	CMP	X0,A
	JNE	<STG5
	MOVE	#>$BB,B
	JMP	<STG_A
STG5	MOVE	#>5,X0		; Check for gain = x5
	CMP	X0,A
	JNE	<STG10
	MOVE	#>$DD,B
	JMP	<STG_A
STG10	MOVE	#>10,X0		; Check for gain = x10
	CMP	X0,A
	JNE	<ERR_SGN
	MOVE	#>$EE,B

STG_A	MOVE	X:(R4)+,A	; Integrator Speed (0 for slow, 1 for fast)
	JCLR	#0,A1,STG_B
	BSET	#8,B1
	BSET	#9,B1
STG_B	MOVE	#$0C3C00,X0
	OR	X0,B
	MOVE	B,Y:<GAIN	; Store the GAIN value for later us

; Send this same value to 15 video processor boards whether they exist or not
	MOVE	#$100000,X0	; Increment value
	DO	#16,STG_LOOP
	MOVE	B,X:SSITX	; Transmit the SSI word
	JSR	<PAL_DLY	; Wait for SSI and PAL to be empty
	ADD	X0,B		; Increment the video processor board number
STG_LOOP

	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<FINISH
ERR_SGN	MOVE	X:(R4)+,A
	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<ERROR

; These are implemented for backward compatibility
HIGAIN  MOVE	#$000204,A
	MOVE	A,X:(R3)+
	MOVE    #'SGN',A	
	MOVE	A,X:(R3)+
	MOVE	#>2,A		; High gain is x 2
	MOVE	A,X:(R3)+
	MOVE	X:<ONE,A	; Fast integrator speed is 1
	MOVE	A,X:(R3)+
	JMP     <PRC_RCV

LOWGAIN	MOVE	#$000204,A
	MOVE	A,X:(R3)+
	MOVE    #'SGN',A	
	MOVE	A,X:(R3)+
	MOVE	#>1,A		; Low gain is x 1
	MOVE	A,X:(R3)+
	MOVE	X:<ONE,A	; Fast integrator speed is 1
	MOVE	A,X:(R3)+
	JMP     <PRC_RCV

; Write an arbitraty control word over the SSI link to any register, any board
; Command syntax is  WRC number, number is 24-bit number to be sent to any board
WR_CNTRL			
	JSR	<SER_ANA	; Set SSI to analog board communication
	JSR	<PAL_DLY	; Wait for the number to be sent
        MOVEP	X:(R4)+,X:SSITX	; Send out the waveform
	JSR	<PAL_DLY	; Wait for SSI and PAL to be empty
	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<FINISH

; Set the video processor boards in DC-coupled diagnostic mode or not
; Command syntax is  SDC #	# = 0 for normal operation
;				# = 1 for DC coupled diagnostic mode
SET_DC	JSR	<SER_ANA	; Set SSI to analog board communication
	MOVE	X:(R4)+,X0
	JSET	#0,X0,SDC_1
	BCLR	#10,Y:<GAIN
	BCLR	#11,Y:<GAIN
	JMP	<SDC_A
SDC_1	BSET	#10,Y:<GAIN
	BSET	#11,Y:<GAIN
SDC_A	MOVE	#$100000,X0	; Increment value
	DO	#15,SDC_LOOP
	MOVEP	Y:GAIN,X:SSITX
	JSR	<PAL_DLY	; Wait for SSI and PAL to be empty
	ADD	X0,B		; Increment the video processor board number
SDC_LOOP
	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<FINISH

; Set a particular bias number, for setting DC bias voltages and 
;   video processor offsets: SBN  #BOARD  #DAC  voltage
; Command syntax is  SBN  #video_board  #DAC_number  #voltage
;				#video_board is from 0 to 15
;				#DAC_number is from 0 to 15
;				#voltage is from 0 to 4095
SET_BIAS_NUMBER			; Set bias number
	JSR	<SER_ANA	; Set SSI to analog board communication
	MOVE	X:(R4)+,A	; First argument is board number, 0 to 15
	REP	#20
	LSL	A
	MOVE	A,X0
	MOVE	X:(R4)+,A	; Second argument is DAC number, 0 to 15
	REP	#14
	LSL	A
	OR	X0,A
	MOVE	X:(R4)+,B	; Third argument is 'VID' or 'CLK' string
	MOVE	#'VID',X0
	CMP	X0,B
	JNE	<CLK_DRV
	BSET	#19,A1		; Set bits to mean video processor DAC
	BSET	#18,A1
	JMP	<VID_BRD
CLK_DRV	MOVE	#'CLK',X0
	CMP	X0,B
	JNE	<ERR_SBN
VID_BRD	MOVE	A,X0
	MOVE	X:(R4)+,A	; Fourth argument is voltage value, 0 to $fff
	MOVE	#$000FFF,Y0	; Mask off just 12 bits to be sure
	AND	Y0,A
	OR	X0,A
	MOVEP	A,X:SSITX	; Write the number to the DAC
	JSR	<PAL_DLY	; Wait for the number to be sent
	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<FINISH
ERR_SBN	MOVE	X:(R4)+,A	; Read and discard the fourth argument
	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<ERROR

; Specify the MUX value to be output on the clock driver board
; Command syntax is  SMX  #clock_driver_board #MUX1 #MUX2
;				#clock_driver_board from 0 to 15
;				#DAC from 0 to 23
SET_MUX	JSR	<SER_ANA	; Set SSI to analog board communication
	MOVE	X:(R4)+,A	; Clock driver board number
	REP	#20
	LSL	A
	MOVE	#$003000,X0
	OR	X0,A
	MOVE	A,X1		; Move here for storage

; Get the first MUX number
	MOVE	X:(R4)+,A	; MUX number
	MOVE	A,B
	MOVE	#>7,X0
	AND	X0,B
	MOVE	#>$18,X0
	AND	X0,A
	JNE	<SMX_1		; Test for 0 <= MUX number <= 7
	BSET	#3,B1
	JMP	<SMX_A
SMX_1	MOVE	#>$8,X0
	CMP	X0,A		; Test for 8 <= MUX number <= 15
	JNE	<SMX_2
	BSET	#4,B1
	JMP	<SMX_A
SMX_2	MOVE	#>$10,X0
	CMP	X0,A		; Test for 16 <= MUX number <= 23
	JNE	<ERR_SMX
	BSET	#5,B1
SMX_A	OR	X1,B1		; Add prefix to MUX numbers
	MOVE	B1,Y1

; Add on the second MUX number
	MOVE	X:(R4)+,A	; Get the next MUX #
	REP	#6
	LSL	A
	MOVE	A,B
	MOVE	#$1C0,X0
	AND	X0,B
	MOVE	Y:<C600,X0
	AND	X0,A
	JNE	<SMX_3		; Test for 0 <= MUX number <= 7
	BSET	#9,B1
	JMP	<SMX_B
SMX_3	MOVE	#>$200,X0
	CMP	X0,A		; Test for 8 <= MUX number <= 15
	JNE	<SMX_4
	BSET	#10,B1
	JMP	<SMX_B
SMX_4	MOVE	#>$400,X0
	CMP	X0,A		; Test for 16 <= MUX number <= 23
	JNE	<ERR_SM2
	BSET	#11,B1
SMX_B	ADD	Y1,B		; Add prefix to MUX numbers

	MOVEP	B1,X:SSITX
	JSR	<PAL_DLY	; Delay for all this to happen
	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<FINISH
ERR_SMX	MOVE	X:(R4)+,A
ERR_SM2	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<ERROR

; Ramp up CCD clocks for testing boards
TST_CLK	JCLR	#0,Y:<TOGGLE,T_EXE
	BCLR	#0,Y:<TOGGLE
	MOVE	#$020002,A	; Reply 'DON' to the host computer
	MOVE	A,X:(R3)+
	MOVE	#'DON',A
	MOVE	A,X:(R3)+
	MOVE	#$000202,A	; Return to here after the "DON' is sent
	MOVE	A,X:(R3)+
	MOVE	#'TCK',A
	MOVE	A,X:(R3)+
	JMP	<PRC_RCV	; Go process these commands

T_EXE	BSET	#0,Y:<TOGGLE	; Make the 'DON's be processed next call to TCK
	JSR	<GET_RCV	; Check for FO or SSI commands
	JCS	<CHK_SSI	; Continue IDLE if no commands received
	JSR	<SER_ANA	; Set SSI to analog board communication
	JSR	<PAL_DLY	; Wait for the number to be sent
	MOVE	#$002FFF,B	; Set clock driver switches all high
	MOVE	B,X:(R6)

; Initialize registers
	MOVE    #$200000,A1	; Clock driver is jumpered to board #2
	MOVE    #$8000,X0	; Board select field, cycled from 0 to 11
	MOVE    X:<ONE,Y0	; Voltage increment
	MOVE    #$200FFF,Y1	; Mask to restore clock selection to zero

; Initialize DACs to zero, and delay to display minimum DAC value on scope
	DO	#24,CK0		; Loop through the 24 DACs on the board
	MOVEP	A1,X:SSITX	; Write the number to the DAC
	DO	#100,L_TCK_DLY0	; Wait for DAC serial word to be transmitted
	NOP
L_TCK_DLY0
	ADD	X0,A		; Increment DAC number
CK0
	AND	Y1,A		; Mask back to first DAC on board
	JSR	<TCK_LVL

; Cycle through remaining voltages
	DO      #4095,CK2	; Loop through 4095 DAC voltages
	DO	#24,CK1		; Loop through the 24 DACs on the board
	MOVEP	A1,X:SSITX	; Write the number to the DAC
	DO	#100,L_TCK_DLY1
	NOP
L_TCK_DLY1
	ADD	X0,A		; Increment DAC number
CK1
	ADD     Y0,A		; Increment voltage
	AND	Y1,A		; Mask back to first DAC on board
CK2
	JSR	<TCK_LVL

; Switch clocks to low voltages and repeat the process
	MOVE	#$002000,B	; Set clock driver switches all low
	MOVE	B,X:(R6)
	MOVE    #$204000,A1	; Clock driver is jumpered to board #2
	MOVE    #$204FFF,Y1	; Mask to restore clock selection to zero

; Initialize DACs to zero, and delay to display minimum DAC value on scope
	DO	#24,CK5		; Loop through the 24 DACs on the board
	MOVEP	A1,X:SSITX	; Write the number to the DAC
	DO	#100,L_TCK_DLY2	; Wait for DAC serial word to be transmitted
	NOP
L_TCK_DLY2
	ADD	X0,A		; Increment DAC number
CK5
	AND	Y1,A		; Mask back to first DAC on board
	JSR	<TCK_LVL
	DO      #4095,CK4	; Loop through 4095 DAC voltages
	DO	#24,CK3		; Loop through the 24 DACs on the board
	MOVEP	A1,X:SSITX	; Write the number to the DAC
	DO	#100,L_TCK_DLY4	; Wait for DAC serial word to be transmitted
	NOP
L_TCK_DLY4
	ADD	X0,A		; Increment DAC number
CK3
	ADD     Y0,A		; Increment voltage
	AND	Y1,A		; Mask back to first DAC on board
CK4
	JSR	<TCK_LVL

; Return timing board to normal utility board communication 
	JSR	<SER_UTL	; Return SSI to utility board communication
	JSR	<PAL_DLY	; Wait for the number to be sent
	JMP	<T_EXE		; Do it again

; Delay by enough to see a nice pedestal on the scope at max and min voltages
TCK_LVL	DO	#4095,L_TCK_LEVEL3
	JSR	<PAL_DLY
	JSR	<PAL_DLY
	NOP
L_TCK_LEVEL3
	RTS

; ***********  DATA AREAS - READOUT PARAMETERS AND WAVEFORMS  ************

; Command table - make sure there are exactly 32 entries in it
	IF	DOWNLOAD 	
	ORG	X:COM_TBL,X:COM_TBL			; Download address
	ELSE			
        ORG     P:COM_TBL,P:APL_NUM*N_W_APL+APL_LEN+$200 	; EEPROM address
	ENDIF
	DC	'IDL',IDL  	; Put CCD in IDLE mode    
	DC	'STP',STP  	; Exit IDLE mode
	DC	'SBV',SETBIAS 	; Set DC bias supply voltages  
	DC	'RDC',RDCCD 	; Begin CCD readout    
	DC	'CLR',CLEAR  	; Fast clear the CCD   
	DC	'SGN',ST_GAIN  	; Set video processor gain     
	DC	'WRC',WR_CNTRL	; Write control word over SSI link
	DC	'SDC',SET_DC	; Set DC coupled diagnostic mode
	DC	'SBN',SET_BIAS_NUMBER	; Set bias number
	DC	'SMX',SET_MUX	; Set clock driver MUX output
	DC	'TCK',TST_CLK	; Ramp pattern on CCD clock driver for test
	DC	'ABR',ABORT	; Abort exposure readout
	DC	'CRD',CONT_RD	; Continue reading out
	DC	'DON',START	; Nothing special
	DC	'CSW',CLR_SWS	; Clear analog switches to reduce power drain
	DC	'TRM',TEST_MEM	; Test memory, for use on SunOS

; These two are included for backward compatability
	DC	'HGN',HIGAIN  	; Set video processor to x2 gain      
	DC	'LGN',LOWGAIN   ; Set video processor to x1 gain   
	DC	0,START,0,START,0,START,0,START
	DC	0,START,0,START,0,START,0,START
	DC	0,START,0,START,0,START,0,START
	DC	0,START,0,START

	IF	DOWNLOAD
	ORG	Y:0,Y:0		; Download address
	ELSE
	ORG     Y:0,P:		; EEPROM address continues from P: above
	ENDIF
GAIN	DC	0		; Video processor gain and integrator speed
NSR     DC      44   	 	; Number Serial Read, prescan + image + bias
NPR     DC      80	     	; Number Parallel Read of each readout only
NSCLR   DC      300    		; To clear serial register
NPCLR   DC      400	    	; To clear parallel register
NSBIN   DC      1       	; Serial binning parameter (not used)
NPBIN   DC      1       	; Parallel binning parameter (not used)
TOGGLE	DC	1		; Toggling bit for executing commands
CFF	DC	$FF		; A constant for the test memory command
CFFFFFF	DC	$FFFFFF
C555555	DC	$555555
CAAAAAA	DC	$AAAAAA
C600	DC	$600	
C1A00	DC	$1A00
C1F00	DC	$1F00
C100	DC	$100
C0181	DC	$0181
C3F00	DC	$3F00
C40f	DC	$40f
C841	DC	$841
C9d7	DC	$9d7

;  Miscellaneous definitions for CCD operation
TST_DAT	DC	0		; Temporary definition for test images

; Define switch state bits for the CCD clocks of the EEV CCD
RL	EQU	0	; Reset output node
RH	EQU	1
SI1L	EQU	0	; Storage and image register, phase #1
SI1H	EQU	2
SI2L	EQU	0	; Storage and image register, phase #2
SI2H	EQU	4
SI3L	EQU	0	; Storage and image register, phase #3
SI3H	EQU	8
R1L	EQU	0	; Serial shift register, phase #1
R1H	EQU	$10
R3L	EQU	0	; Serial shift register, phase #2
R3H	EQU	$20
R2L	EQU	0	; Serial shift register, phase #3
R2H	EQU	$40

;  ***  Definitions for Y: memory waveform tables  *****
PARALLEL DC	SERIAL_IDLE-PARALLEL-2  
	DC	CLK+P_DELAY+SI1L+SI2H+SI3H+RH+R1H+R2L+R3L
	DC	CLK+P_DELAY+SI1L+SI2L+SI3H+RH+R1H+R2L+R3L
	DC	CLK+P_DELAY+SI1H+SI2L+SI3H+RH+R1H+R2L+R3L
	DC	CLK+P_DELAY+SI1H+SI2L+SI3L+RH+R1H+R2L+R3L
	DC	CLK+P_DELAY+SI1H+SI2H+SI3L+RH+R1H+R2L+R3L
	DC	CLK+P_DELAY+SI1L+SI2H+SI3L+RH+R1H+R2L+R3L
	DC	CLK+$000000+SI1L+SI2H+SI3L+RL+R1H+R2L+R3L

; Video processor bit definition
;	     xfer, A/D, integ, Pol+, Pol-, DCrestore, rst   (1 => switch open)
SERIAL_IDLE
	DC	SSKIP-SERIAL_IDLE-2
	DC	CLK+SI1L+SI2H+SI3L+RH+R1H+R2H+R3L
	DC	VIDEO+$000000+%1110100	; Change nearly everything
	DC	CLK+SI1L+SI2H+SI3L+RL+R1L+R2H+R3L
	DC	CLK+SI1L+SI2H+SI3L+RL+R1L+R2H+R3H
	DC	CLK+SI1L+SI2H+SI3L+RL+R1L+R2L+R3H
	DC	CLK+SI1L+SI2H+SI3L+RL+R1H+R2L+R3H
	DC	VIDEO+$000000+%1110111	; Stop resetting integrator
	DC	VIDEO+$2e0000+%0000111	; Integrate for 1 microsec
	DC	VIDEO+$000000+%0011011	; Stop Integrate
	DC	CLK+SI1L+SI2H+SI3L+RL+R1H+R2L+R3L
	DC	VIDEO+$000000+%0011011	; Delay for signal to settle
	DC	VIDEO+$000000+%0011011	; Delay for signal to settle
	DC	VIDEO+$2c0000+%0001011	; Integrate for another microsec
	DC	VIDEO+$000000+%0001011	; Continue integrating
	DC	VIDEO+$000000+%0011000	; Stop integrate, A/D is sampling

; Serial clocking waveform for skipping
SSKIP   DC	DACS-SSKIP-2
	DC	CLK+SI1L+SI2H+SI3L+RH+R1H+R2L+R3L
	DC	CLK+SI1L+SI2H+SI3L+RL+R1H+R2L+R3L
	DC	CLK+SI1L+SI2H+SI3L+RL+R1H+R2H+R3L
	DC	CLK+SI1L+SI2H+SI3L+RL+R1L+R2H+R3L
	DC	CLK+SI1L+SI2H+SI3L+RL+R1L+R2H+R3H
	DC	CLK+SI1L+SI2H+SI3L+RL+R1L+R2L+R3H
	DC	CLK+SI1L+SI2H+SI3L+RL+R1H+R2L+R3H
	DC	CLK+SI1L+SI2H+SI3L+RL+R1H+R2L+R3L

; Initialization of clock driver and video processor DACs and switches
DACS	DC	END_DACS-DACS-1
	DC	(CLK2<<8)+R_HI		; R High
	DC	(CLK2<<8)+(1<<14)+R_LO	; R Low
	DC	(CLK2<<8)+(2<<14)+SI_HI	; SI1 High
	DC	(CLK2<<8)+(3<<14)+SI_LO	; SI1 Low
	DC	(CLK2<<8)+(4<<14)+SI_HI	; SI2 High
	DC	(CLK2<<8)+(5<<14)+SI_LO	; SI2 Low
	DC	(CLK2<<8)+(6<<14)+SI_HI	; SI3 High
	DC	(CLK2<<8)+(7<<14)+SI_LO	; SI3 Low
	DC	(CLK2<<8)+(8<<14)+R_HI	; R1 High
	DC	(CLK2<<8)+(9<<14)+R_LO	; R1 Low
	DC	(CLK2<<8)+(10<<14)+R_HI	; R2 High
	DC	(CLK2<<8)+(11<<14)+R_LO	; R2 Low
	DC	(CLK2<<8)+(12<<14)+R_HI	; R3 High
	DC	(CLK2<<8)+(13<<14)+R_LO	; R3 Low

; Set the DACs of the second clock driver board # 3
	DC	(CLK3<<8)+R_HI		; R High
	DC	(CLK3<<8)+(1<<14)+R_LO	; R Low
	DC	(CLK3<<8)+(2<<14)+SI_HI	; SI1 High
	DC	(CLK3<<8)+(3<<14)+SI_LO	; SI1 Low
	DC	(CLK3<<8)+(4<<14)+SI_HI	; SI2 High
	DC	(CLK3<<8)+(5<<14)+SI_LO	; SI2 Low
	DC	(CLK3<<8)+(6<<14)+SI_HI	; SI3 High
	DC	(CLK3<<8)+(7<<14)+SI_LO	; SI3 Low
	DC	(CLK3<<8)+(8<<14)+R_HI	; R1 High
	DC	(CLK3<<8)+(9<<14)+R_LO	; R1 Low
	DC	(CLK3<<8)+(10<<14)+R_HI	; R2 High
	DC	(CLK3<<8)+(11<<14)+R_LO	; R2 Low
	DC	(CLK3<<8)+(12<<14)+R_HI	; R3 High
	DC	(CLK3<<8)+(13<<14)+R_LO	; R3 Low

; Set the DACs of the third clock driver board # 4
	DC	(CLK4<<8)+R_HI		; R High
	DC	(CLK4<<8)+(1<<14)+R_LO	; R Low
	DC	(CLK4<<8)+(2<<14)+SI_HI	; SI1 High
	DC	(CLK4<<8)+(3<<14)+SI_LO	; SI1 Low
	DC	(CLK4<<8)+(4<<14)+SI_HI	; SI2 High
	DC	(CLK4<<8)+(5<<14)+SI_LO	; SI2 Low
	DC	(CLK4<<8)+(6<<14)+SI_HI	; SI3 High
	DC	(CLK4<<8)+(7<<14)+SI_LO	; SI3 Low
	DC	(CLK4<<8)+(8<<14)+R_HI	; R1 High
	DC	(CLK4<<8)+(9<<14)+R_LO	; R1 Low
	DC	(CLK4<<8)+(10<<14)+R_HI	; R2 High
	DC	(CLK4<<8)+(11<<14)+R_LO	; R2 Low
	DC	(CLK4<<8)+(12<<14)+R_HI	; R3 High
	DC	(CLK4<<8)+(13<<14)+R_LO	; R3 Low


; Set gain and integrator speed. x 9.5 gain, fast integrate
	DC	$0c3fee			; Gain, integrate speed, board #0
	DC	$1c3fee			; Gain, integrate speed
	DC	$2c3fee			; Gain, integrate speed
	DC	$3c3fee			; Gain, integrate speed

; Input offset voltages for DC coupling. Target is U4#6 = 24 volts
	DC	$0c0800			; Input offset, ch. A
	DC	$0c8800			; Input offset, ch. B
	DC	$1c0800			; Input offset, ch. A, bd. #1
	DC	$1c8800			; Input offset, ch. B, bd. #1
	DC	$2c0800			; Input offset, ch. A, bd. #2
	DC	$2c8800			; Input offset, ch. B, bd. #2
	DC	$3c0800			; Input offset, ch. A, bd. #3
	DC	$3c8800			; Input offset, ch. B, bd. #3

; Output offset voltages to get around 1000 DN A/D units on a dark frame
	DC	$0c46c0			; Output video offset, ch. A
	DC	$0cc6c0			; Output video offset, ch. B
	DC	$1c46c0			; Output video offset, ch. A, bd. #1
	DC	$1cc6c0			; Output video offset, ch. B, bd. #1
	DC	$2c46c0			; Output video offset, ch. A, bd. #2
	DC	$2cc6c0			; Output video offset, ch. B, bd. #2
	DC	$3c46c0			; Output video offset, ch. A, bd. #3
	DC	$3cc6c0			; Output video offset, ch. B, bd. #3

; DC bias voltages for the EEV39 wavefront sensor CCD chip
	DC	$0d0c8a			; Vod = 24.00 V, pin #2
	DC	$0d8719			; Vrd = 11.00 V, pin #3
	DC	$0f8540			; Vog = -3.4V pin #11 best CTE
	DC	$1d0c8a			; Vod = 24.00 V, pin #1, bd. #1
	DC	$1f8540			; Vog = -3.4V pin #11 best CTE, bd. #1
	DC	$2d0c8a			; Vod = 24.00 V, pin #1, bd. #2
	DC	$2f8540			; Vog = -3.4V pin #11 best CTE, bd. #2
	DC	$3d0c8a			; Vod = 24.00 V, pin #1, bd. #3
	DC	$3f8540			; Vog = -3.4V pin #11 best CTE, bd. #3
END_DACS

; Check for Y: data memory overflow
        IF	@CVS(N,*)>$80
        WARN    'Application Y: data memory is too large!' ; Make sure Y:
	ENDIF						   ;  will not overflow

; The fast serial code with the circulating address register must start on
;    a boundary that is a multiple of the address register modulus.
; Offset $2C0 leaves APL_LEN+$200 words for P: code, $20 wrods for commands, 
;    and $80 words for Y: waveforms above.

	IF	DOWNLOAD
	ORG	Y:$80,Y:$80		; Download address
	ELSE
	ORG     Y:$80,P:APL_NUM*N_W_APL+APL_LEN+$2C0 ; EEPROM address
	ENDIF

;	     xfer, A/D, integ, Pol+, Pol-, DCrestore, rst   (1 => switch open)
SERIAL	DC	CLK+SI1L+SI2H+SI3L+RH+R1H+R2H+R3L
	DC	VIDEO+$000000+%1110100	; Change nearly everything
	DC	CLK+SI1L+SI2H+SI3L+RL+R1L+R2H+R3L
	DC	CLK+SI1L+SI2H+SI3L+RL+R1L+R2H+R3H
	DC	CLK+SI1L+SI2H+SI3L+RL+R1L+R2L+R3H
	DC	CLK+SI1L+SI2H+SI3L+RL+R1H+R2L+R3H
	DC	SXMIT			; Transmit A/D data to host
	DC	VIDEO+$000000+%1110111	; Stop resetting integrator
	DC	VIDEO+$000000+%1110111	; !!! Delay for signal to settle
	DC	VIDEO+$2e0000+%0000111	; Integrate for 1 microsec
	DC	VIDEO+$000000+%0011011	; Stop Integrate
	DC	CLK+SI1L+SI2H+SI3L+RL+R1H+R2L+R3L
	DC	VIDEO+$000000+%0011011	; Delay for signal to settle
	DC	VIDEO+$000000+%0011011	; Delay for signal to settle
	DC	VIDEO+$2e0000+%0001011	; Integrate for another microsec
	DC	VIDEO+$000000+%0011011	; Stop integrate, A/D is sampling
END_SERIAL

; Check for overflow in the EEPROM case
	IF !DOWNLOAD
		IF	@CVS(N,@LCV(L))>(APL_NUM+1)*N_W_APL
	WARN    'EEPROM overflow!'	; Make sure next application
		ENDIF			;  will not be overwritten
	ENDIF

	ENDSEC		; End of section TIMTEST

;  End of program
	END