; Miscellaneous definitions
VIDEO	EQU     $000000	; Video board select = 0
CLK2	EQU     $002000 ; Select bottom of clock driver board 
CLK3	EQU     $003000 ; Select top of clock driver board
CLK4	EQU     $004000 ; Select DC bias board
AD	EQU	$000001	; Bit to start A/D conversion
XFER	EQU	$000002	; Bit to transfer A/D counts into the A/D FIFO
CLK_ZERO EQU	0	; Zero volts out on clock driver line
SXMIT	EQU	$00F0E0	; Transmit 8 pixels from two coadder boards

; Various delay parameters
VP_DLY	EQU	$1C0000	; Video delay time for 2.0 microsec/pixel
VP_DLY_PT EQU	$B80000	; Pass through video delay time for 10.0 microsec/pixel
DLY0	EQU	$280000	; Pixel readout delay parameter
DLY1	EQU	$400000	; Frame sync delay parameter
DLY2	EQU	$980000
DLGR	EQU	$980000	; Delay for Global Reset

DLY5	EQU	$280000	; Pixel readout delay parameters
DLY6	EQU	$0C0000
DLY7	EQU	$200000
DLY8	EQU	$0C0000


; Values for displaying clocks on Logic Analyzer with CCD clock driver board
;MAX_V	EQU	10.0		; Maximum voltage from the clock driver board
;CLK_HI	EQU	6.5		; High Clock voltage
;CLK_LO	EQU	5.0		; Low Clock voltage

;; Values for IR clock driver board when the clock driver board is jumpered for
;;   negative voltages, and these voltages here are absolute values. 
;MAX_V	EQU	 7.5		; Maximum voltage from clock driver board
;MAX_V2	EQU	15.0		; 2 x MAX_V
;CLK_HI	EQU	 7.5		; High Clock voltage
;CLK_LO	EQU	 1.5		; Low Clock voltage

; Values for IR clock driver board when the clock driver board is jumpered for
;   bipolar operation (as it is for the HAWAII-1R)
MAX_V	EQU	 7.5		; Maximum voltage from clock driver board
MAX_V2	EQU	15.0		; 2 x MAX_V
CLK_HI	EQU	-7.5		; High Clock voltage
CLK_LO	EQU	-1.5		; Low Clock voltage

; Put all the waveform tables in SRAM
	IF	@SCP("DOWNLOAD","HOST")
	ORG	Y:$100,Y:$100				; Download address
	ELSE
	ORG	Y:$100,P:APL_NUM*N_W_APL+APL_LEN+$340	; ROM address
	ENDIF

; Define switch state bits for CLK2 = bottom of clock board
SSYNC	EQU     1		; Slow Sync
S1	EQU     2		; Slow phase 1
S2	EQU     4		; Slow phase 1
SOE	EQU     8		; Odd/Even row select
RDES	EQU     $10		; Row deselect
VRSTOFF	EQU     $20		; Global reset = VrstG
VRSTR	EQU     $40		; Row reset bias
VROWON	EQU	$80		; Bias to row enable

; Define switch state bits for CLK3 = top of clock board
FSYNC	EQU     1		; Fast sync
F1	EQU	2		; Fast phase 1
F2	EQU	4		; Fast phase 2


; Copy of the clocking bit definition for easy reference
;	DC	CLK2+DELAY+SSYNC+S1+S2+SOE+RDES+VRSTOFF+VRSTR+VROWON
;	DC	CLK3+DELAY+FSYNC+F1+F2

FRAME_INIT
	DC	FRAME_INIT_RESET-FRAME_INIT-2
	DC	CLK2+DLY1+SSYNC+S1+S2+SOE+RDES+VRSTOFF+VRSTR+000000
	DC	CLK2+DLY1+00000+S1+S2+SOE+RDES+VRSTOFF+VRSTR+000000
	DC	CLK2+DLY1+SSYNC+S1+S2+SOE+RDES+VRSTOFF+VRSTR+000000
	DC	CLK2+DLGR+SSYNC+S1+S2+SOE+RDES+VRSTOFF+VRSTR+000000
	DC	CLK2+DLY1+SSYNC+S1+S2+SOE+RDES+VRSTOFF+VRSTR+000000
	DC	CLK2+DLY1+SSYNC+00+S2+SOE+RDES+VRSTOFF+VRSTR+000000
	DC	CLK2+DLY1+SSYNC+S1+S2+SOE+RDES+VRSTOFF+VRSTR+000000

FRAME_INIT_RESET
	DC	CLOCK_ROW_1-FRAME_INIT_RESET-2
	DC	CLK2+DLY1+SSYNC+S1+S2+SOE+RDES+VRSTOFF+VRSTR+000000
	DC	CLK2+DLY1+00000+S1+S2+SOE+RDES+VRSTOFF+VRSTR+000000
	DC	CLK2+DLY1+SSYNC+S1+S2+SOE+RDES+VRSTOFF+VRSTR+000000
	DC	CLK2+DLGR+SSYNC+S1+S2+SOE+RDES+0000000+VRSTR+000000
	DC	CLK2+DLY1+SSYNC+S1+S2+SOE+RDES+VRSTOFF+VRSTR+000000
	DC	CLK2+DLY1+SSYNC+00+S2+SOE+RDES+VRSTOFF+VRSTR+000000
	DC	CLK2+DLY1+SSYNC+S1+S2+SOE+RDES+VRSTOFF+VRSTR+000000

CLOCK_ROW_1
	DC	CLOCK_ROW_2-CLOCK_ROW_1-2
	DC	CLK2+DLY1+SSYNC+S1+00+000+RDES+VRSTOFF+VRSTR+000000
	DC	CLK3+DLY0+00000+F1+F2
	DC	CLK3+DLY0+FSYNC+F1+F2
	DC	CLK3+DLY0+FSYNC+00+F2
	DC	CLK3+DLY2+FSYNC+F1+F2
	DC	CLK2+DLY1+SSYNC+S1+00+000+RDES+VRSTOFF+VRSTR+000000

CLOCK_ROW_2
	DC	CLOCK_ROW_3-CLOCK_ROW_2-2
	DC	CLK2+DLY2+SSYNC+S1+00+SOE+RDES+VRSTOFF+VRSTR+000000
	DC	CLK3+DLY0+00000+F1+F2
	DC	CLK3+DLY0+FSYNC+F1+F2
	DC	CLK3+DLY0+FSYNC+00+F2
	DC	CLK3+DLY2+FSYNC+F1+F2
	DC	CLK2+DLY1+SSYNC+S1+00+SOE+RDES+VRSTOFF+VRSTR+000000

CLOCK_ROW_3
	DC	CLOCK_ROW_4-CLOCK_ROW_3-2
	DC	CLK2+DLY1+SSYNC+00+S2+000+RDES+VRSTOFF+VRSTR+000000
	DC	CLK3+DLY0+00000+F1+F2
	DC	CLK3+DLY0+FSYNC+F1+F2
	DC	CLK3+DLY0+FSYNC+00+F2
	DC	CLK3+DLY2+FSYNC+F1+F2
	DC	CLK2+DLY1+SSYNC+00+S2+000+RDES+VRSTOFF+VRSTR+000000

CLOCK_ROW_4
	DC	CLOCK_COLUMN-CLOCK_ROW_4-2
	DC	CLK2+DLY2+SSYNC+00+S2+SOE+RDES+VRSTOFF+VRSTR+000000
	DC	CLK3+DLY0+00000+F1+F2
	DC	CLK3+DLY0+FSYNC+F1+F2
	DC	CLK3+DLY0+FSYNC+00+F2
	DC	CLK3+DLY2+FSYNC+F1+F2
	DC	CLK2+DLY1+SSYNC+00+S2+SOE+RDES+VRSTOFF+VRSTR+000000

CLOCK_COLUMN
	DC	END_CLOCK_COLUMN-CLOCK_COLUMN-2
	DC	CLK3+DLY5+FSYNC+00+F2
	DC	CLK3+DLY6+FSYNC+F1+F2
	DC	CLK3+DLY5+FSYNC+F1+00
	DC	CLK3+0000+FSYNC+F1+F2
END_CLOCK_COLUMN


; The first waveform table here does A/D conversion twice without writing
;   The A/D values to the latch with XFER. The second waveform table does
;   the A/D conversion and writes the previous 2 A/D values to the latch
;   because of the pipeline delay in the ADS937 A/D converter. 
CLOCK_COL_AND_READ_NO_XFER
	DC	END_CLOCK_COL_AND_READ_NO_XFER-CLOCK_COL_AND_READ_NO_XFER-2
	DC	CLK3+DLY7+FSYNC+F1+00
	DC	VIDEO+VP_DLY+AD
	DC	VIDEO
	DC	CLK3+DLY8+FSYNC+F1+F2
	DC	CLK3+DLY7+FSYNC+00+F2
	DC	VIDEO+VP_DLY+AD
	DC	VIDEO
	DC	CLK3+FSYNC+F1+F2
END_CLOCK_COL_AND_READ_NO_XFER

CLOCK_COL_AND_READ
	DC	END_CLOCK_COL_AND_READ-CLOCK_COL_AND_READ-2
	DC	CLK3+DLY7+FSYNC+F1+00
	DC	VIDEO+VP_DLY+AD+XFER
	DC	VIDEO
	DC	CLK3+DLY8+FSYNC+F1+F2
	DC	CLK3+DLY7+FSYNC+00+F2
	DC	VIDEO+VP_DLY+AD+XFER
	DC	VIDEO
	DC	CLK3+FSYNC+F1+F2
END_CLOCK_COL_AND_READ



; PT => Pass Through mode, wherein the coadder boards pass pixel data as
;   quickly as possible to the timing board for transmission to the host
CLOCK_COL_AND_READ_PT_NO_XFER
	DC	END_CLOCK_COL_AND_READ_PT_NO_XFER-CLOCK_COL_AND_READ_PT_NO_XFER-2
	DC	CLK3+VP_DLY_PT+FSYNC+F1+00
	DC	VIDEO+$100000+AD		; Delay needed for the 
	DC	VIDEO				;   coadder to get started
	DC	VIDEO
	DC	CLK3+DLY8+FSYNC+F1+F2
	DC	CLK3+VP_DLY_PT+FSYNC+00+F2
	DC	VIDEO+$100000+AD
	DC	VIDEO
	DC	VIDEO
	DC	CLK3+FSYNC+F1+F2
END_CLOCK_COL_AND_READ_PT_NO_XFER

CLOCK_COL_AND_READ_PT
	DC	END_CLOCK_COL_AND_READ_PT-CLOCK_COL_AND_READ_PT-2
	DC	CLK3+VP_DLY_PT+FSYNC+F1+00
	DC	VIDEO+$100000+AD+XFER
	DC	VIDEO
	DC	SXMIT
	DC	CLK3+DLY8+FSYNC+F1+F2
	DC	CLK3+VP_DLY_PT+FSYNC+00+F2
	DC	VIDEO+$100000+AD+XFER
	DC	VIDEO
	DC	SXMIT
	DC	CLK3+FSYNC+F1+F2
END_CLOCK_COL_AND_READ_PT



; These are the waveforms for row-by-row reset, assert VrstR and VrowON
CLOCK_ROW_1_RESET
	DC	CLOCK_ROW_2_RESET-CLOCK_ROW_1_RESET-2
	DC	CLK2+DLY1+SSYNC+S1+00+000+RDES+VRSTOFF+VRSTR+000000
	DC	CLK2+DLY1+SSYNC+S1+00+000+RDES+VRSTOFF+00000+VROWON
	DC	CLK2+DLY1+SSYNC+S1+00+000+RDES+VRSTOFF+VRSTR+VROWON
	DC	CLK2+DLY1+SSYNC+S1+00+000+RDES+VRSTOFF+VRSTR+000000
	DC	CLK3+DLY0+00000+F1+F2
	DC	CLK3+DLY0+FSYNC+F1+F2
	DC	CLK3+DLY0+FSYNC+00+F2
	DC	CLK3+DLY2+FSYNC+F1+F2
	DC	CLK2+DLY1+SSYNC+S1+00+000+RDES+VRSTOFF+VRSTR+000000

CLOCK_ROW_2_RESET
	DC	CLOCK_ROW_3_RESET-CLOCK_ROW_2_RESET-2
	DC	CLK2+DLY2+SSYNC+S1+00+SOE+RDES+VRSTOFF+VRSTR+000000
	DC	CLK2+DLY1+SSYNC+S1+00+SOE+RDES+VRSTOFF+00000+VROWON
	DC	CLK2+DLY1+SSYNC+S1+00+SOE+RDES+VRSTOFF+VRSTR+VROWON
	DC	CLK2+DLY1+SSYNC+S1+00+SOE+RDES+VRSTOFF+VRSTR+000000
	DC	CLK3+DLY0+00000+F1+F2
	DC	CLK3+DLY0+FSYNC+F1+F2
	DC	CLK3+DLY0+FSYNC+00+F2
	DC	CLK3+DLY2+FSYNC+F1+F2
	DC	CLK2+DLY1+SSYNC+S1+00+SOE+RDES+VRSTOFF+VRSTR+000000

CLOCK_ROW_3_RESET
	DC	CLOCK_ROW_4_RESET-CLOCK_ROW_3_RESET-2
	DC	CLK2+DLY1+SSYNC+00+S2+000+RDES+VRSTOFF+VRSTR+000000
	DC	CLK2+DLY1+SSYNC+00+S2+000+RDES+VRSTOFF+00000+VROWON
	DC	CLK2+DLY1+SSYNC+00+S2+000+RDES+VRSTOFF+VRSTR+VROWON
	DC	CLK2+DLY1+SSYNC+00+S2+000+RDES+VRSTOFF+VRSTR+000000
	DC	CLK3+DLY0+00000+F1+F2
	DC	CLK3+DLY0+FSYNC+F1+F2
	DC	CLK3+DLY0+FSYNC+00+F2
	DC	CLK3+DLY2+FSYNC+F1+F2
	DC	CLK2+DLY1+SSYNC+00+S2+000+RDES+VRSTOFF+VRSTR+000000

CLOCK_ROW_4_RESET
	DC	READ_LAST_EIGHT_PIXELS-CLOCK_ROW_4_RESET-2
	DC	CLK2+DLY2+SSYNC+00+S2+SOE+RDES+VRSTOFF+VRSTR+000000
	DC	CLK2+DLY1+SSYNC+00+S2+SOE+RDES+VRSTOFF+00000+VROWON
	DC	CLK2+DLY1+SSYNC+00+S2+SOE+RDES+VRSTOFF+VRSTR+VROWON
	DC	CLK2+DLY1+SSYNC+00+S2+SOE+RDES+VRSTOFF+VRSTR+000000
	DC	CLK3+DLY0+00000+F1+F2
	DC	CLK3+DLY0+FSYNC+F1+F2
	DC	CLK3+DLY0+FSYNC+00+F2
	DC	CLK3+DLY2+FSYNC+F1+F2
	DC	CLK2+DLY1+SSYNC+00+S2+SOE+RDES+VRSTOFF+VRSTR+000000

; These two waveforms tables only do A/D conversions and transfers of
;   latched data to the FIFOs. They are executed once at the end of reading
;   the array to get the two last A/D values left over because of the 
;   pipeline delay. 
READ_LAST_EIGHT_PIXELS
	DC	SXMIT_LAST_EIGHT_PIXELS-READ_LAST_EIGHT_PIXELS-2
	DC	VIDEO+VP_DLY
	DC	VIDEO+VP_DLY
	DC	VIDEO+AD+XFER
	DC	VIDEO+VP_DLY
	DC	VIDEO+VP_DLY
	DC	VIDEO+AD+XFER
	DC	VIDEO+VP_DLY

SXMIT_LAST_EIGHT_PIXELS
	DC	ZERO_BIASES-SXMIT_LAST_EIGHT_PIXELS-2
	DC	VIDEO+VP_DLY_PT
	DC	VIDEO+$100000+AD+XFER
	DC	VIDEO
	DC	SXMIT
	DC	VIDEO+VP_DLY_PT
	DC	VIDEO+$100000+AD+XFER
	DC	VIDEO
	DC	SXMIT

;  Zero out the DC biases during the power-on sequence
ZERO_BIASES
	DC	CLOCKS-ZERO_BIASES-1
	DC	(CLK2<<8)+(0<<14)+CLK_ZERO
	DC	(CLK2<<8)+(2<<14)+CLK_ZERO
	DC	(CLK2<<8)+(4<<14)+CLK_ZERO
	DC	(CLK2<<8)+(6<<14)+CLK_ZERO
	DC	(CLK2<<8)+(8<<14)+CLK_ZERO
	DC	(CLK2<<8)+(10<<14)+CLK_ZERO
	DC	(CLK2<<8)+(12<<14)+CLK_ZERO
	DC	(CLK2<<8)+(14<<14)+CLK_ZERO
	DC	(CLK2<<8)+(16<<14)+CLK_ZERO
	DC	(CLK2<<8)+(18<<14)+CLK_ZERO
	DC	(CLK2<<8)+(20<<14)+CLK_ZERO
	DC	(CLK2<<8)+(22<<14)+CLK_ZERO
	DC	(CLK2<<8)+(24<<14)+CLK_ZERO
	DC	(CLK2<<8)+(26<<14)+CLK_ZERO
	DC	(CLK2<<8)+(28<<14)+CLK_ZERO
	DC	(CLK2<<8)+(30<<14)+CLK_ZERO
	DC	(CLK2<<8)+(32<<14)+CLK_ZERO
	DC	(CLK2<<8)+(34<<14)+CLK_ZERO
	DC	(CLK2<<8)+(36<<14)+CLK_ZERO
	DC	(CLK2<<8)+(38<<14)+CLK_ZERO
	DC	(CLK2<<8)+(40<<14)+CLK_ZERO
	DC	(CLK2<<8)+(42<<14)+CLK_ZERO
	DC	(CLK2<<8)+(44<<14)+CLK_ZERO
	DC	(CLK2<<8)+(46<<14)+CLK_ZERO

	DC	(CLK4<<8)+(0<<14)+CLK_ZERO
	DC	(CLK4<<8)+(2<<14)+CLK_ZERO
	DC	(CLK4<<8)+(4<<14)+CLK_ZERO
	DC	(CLK4<<8)+(6<<14)+CLK_ZERO
	DC	(CLK4<<8)+(8<<14)+CLK_ZERO
	DC	(CLK4<<8)+(10<<14)+CLK_ZERO
	DC	(CLK4<<8)+(12<<14)+CLK_ZERO
	DC	(CLK4<<8)+(14<<14)+CLK_ZERO
	DC	(CLK4<<8)+(16<<14)+CLK_ZERO
	DC	(CLK4<<8)+(18<<14)+CLK_ZERO
	DC	(CLK4<<8)+(20<<14)+CLK_ZERO
	DC	(CLK4<<8)+(22<<14)+CLK_ZERO
	DC	(CLK4<<8)+(24<<14)+CLK_ZERO
	DC	(CLK4<<8)+(26<<14)+CLK_ZERO
	DC	(CLK4<<8)+(28<<14)+CLK_ZERO
	DC	(CLK4<<8)+(30<<14)+CLK_ZERO
	DC	(CLK4<<8)+(32<<14)+CLK_ZERO
	DC	(CLK4<<8)+(34<<14)+CLK_ZERO
	DC	(CLK4<<8)+(36<<14)+CLK_ZERO
	DC	(CLK4<<8)+(38<<14)+CLK_ZERO
	DC	(CLK4<<8)+(40<<14)+CLK_ZERO
	DC	(CLK4<<8)+(42<<14)+CLK_ZERO
	DC	(CLK4<<8)+(44<<14)+CLK_ZERO
	DC	(CLK4<<8)+(46<<14)+CLK_ZERO

; Initialize all DACs, starting with the clock driver ones
CLOCKS    DC      BIASES-CLOCKS-1

; Clocking voltages
	DC	(CLK2<<8)+(0<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #1 SSYNC
	DC	(CLK2<<8)+(1<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(2<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #2 S1
	DC	(CLK2<<8)+(3<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(4<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #3 S2
	DC	(CLK2<<8)+(5<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(6<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #4 SOE
	DC	(CLK2<<8)+(7<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(8<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #5 RDES
	DC	(CLK2<<8)+(9<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(10<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #6 VRSTOFF
	DC	(CLK2<<8)+(11<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(12<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #7 VRSTR
	DC	(CLK2<<8)+(13<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(14<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #8 VROWON
	DC	(CLK2<<8)+(15<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)

; Clocking voltages for the top half of the board
	DC	(CLK2<<8)+(24<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #13 FSYNC
	DC	(CLK2<<8)+(25<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(26<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #14 F1
	DC	(CLK2<<8)+(27<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)
	DC	(CLK2<<8)+(28<<14)+@CVI((CLK_HI+MAX_V)/MAX_V2*4095)	; Pin #15 F2
	DC	(CLK2<<8)+(29<<14)+@CVI((CLK_LO+MAX_V)/MAX_V2*4095)

; Aladdin DC bias voltage definition
VGGCL	EQU	-1.5		; Column Clamp Clock, warm 
VDDCL	EQU	-3.8		; Column Clamp Bias
VDDUC	EQU	-3.8		; Negative Unit Cell Bias
VNROW	EQU	-6.0		; Negative row supply
VNCOL	EQU	-6.0		; Negative column supply
VDDOUT	EQU	-1.5		; Drain voltage for drivers
VDETCOM	EQU	-3.9		; Detector Common
IREF	EQU	-5.0		; Reference current for Iidle and Islew
VSSOUT	EQU	 1.0		; Source follower load voltage

; DC Bias voltages assignments for the DC bias board. The DC bias board is strapped
;   for bipolar outputs to accomodate the +1.0 volt VssOUT required for the video
;   source followers. The rail voltage is MAX_V = 7.5 volts. MAX_V2 = 2 x MAX_V = 15.0

BIASES	DC	START_UP-BIASES-1
	DC	(CLK4<<8)+(1<<14)+@CVI((VGGCL+MAX_V)/MAX_V2*4095)	; Pin #1 VggCl
	DC	(CLK4<<8)+(3<<14)+@CVI((VDDCL+MAX_V)/MAX_V2*4095)	; Pin #2 VddCl
	DC	(CLK4<<8)+(5<<14)+@CVI((VDDUC+MAX_V)/MAX_V2*4095)	; Pin #3 VddUC
	DC	(CLK4<<8)+(7<<14)+@CVI((VNROW+MAX_V)/MAX_V2*4095) 	; Pin #4 VnRow
	DC	(CLK4<<8)+(9<<14)+@CVI((VNCOL+MAX_V)/MAX_V2*4095)	; Pin #5 VnCol
	DC	(CLK4<<8)+(11<<14)+@CVI((VDDOUT+MAX_V)/MAX_V2*4095)	; Pin #6 VddOut
	DC	(CLK4<<8)+(13<<14)+@CVI((VDETCOM+MAX_V)/MAX_V2*4095)	; Pin #7 VdetCom
	DC	(CLK4<<8)+(15<<14)+@CVI((IREF+MAX_V)/MAX_V2*4095)	; Pin #8 Iref
	DC	(CLK4<<8)+(17<<14)+@CVI((+VSSOUT+MAX_V)/MAX_V2*4095)	; Pin #9 VssOut

; DAC settings for the video offsets with two coadder boards installed

OFFSET	EQU	$000
OFFSET0	EQU	OFFSET
OFFSET1	EQU	OFFSET
OFFSET2	EQU	OFFSET
OFFSET3	EQU	OFFSET
OFFSET4	EQU	OFFSET
OFFSET5	EQU	OFFSET
OFFSET6	EQU	OFFSET
OFFSET7	EQU	OFFSET

OFF_0		DC    $0c0000+OFFSET0	; Input offset board #0, channel A coadder
OFF_1		DC    $0c4000+OFFSET1	; Input offset board #0, channel B coadder
OFF_2		DC    $0c8000+OFFSET2	; Input offset board #0, channel C coadder
OFF_3		DC    $0cc000+OFFSET3	; Input offset board #0, channel D coadder

OFF_4		DC    $1c0000+OFFSET4	; Input offset board #1, channel A coadder
OFF_5		DC    $1c4000+OFFSET5	; Input offset board #1, channel B coadder
OFF_6		DC    $1c8000+OFFSET6	; Input offset board #1, channel C coadder
OFF_7		DC    $1cc000+OFFSET7	; Input offset board #1, channel D coadder

START_UP
	DC	END_WAVEFORMS-START_UP-1
	DC	(CLK4<<8)+(7<<14)+@CVI((VNROW+MAX_V)/MAX_V2*4095) 	; Pin #4 VnRow
	DC	(CLK4<<8)+(9<<14)+@CVI((VNCOL+MAX_V)/MAX_V2*4095)	; Pin #5 VnCol

END_WAVEFORMS