Pinouts for SDSU Gen II controller to control an EEV 39 WFS chip

The lists below assume that the storage and image sections of the chip
are wired separately so frame transfer operations can be supported. The
pin assignments listed match the DSP software provided for reading out
the EEV39 chip. 

Wiring of DB37 connector on the clock driver board 

Pin #
  1	RL	Reset left output node
  2	S1	Storage register, phase #1
  3	S2	Storage register, phase #2
  4	S3	Storage register, phase #3
  5	R1	Serial shift register, phase #1
  6	R3	Serial shift register, phase #3
  7	R2	Serial shift register, phase #2
  8	I3	Imaging register, phase #3
  9	I2	Imaging register, phase #2
 10	I1	Imaging register, phase #1
 11	RR	Reset right output node
Pins 22-32 are ground pins. 



Wiring of the DB15 connector on the video processor board, board #0

Pin #
  1	VOD	Output drain
  3	VRD	Reset drain
 11	VOG	Output Gate
Pins 16-25 are ground pins.


Wiring of the DB15 connector on the video processor board, board #1

Pin #
  1	VOD	Output drain
 11	VOG	Output Gate