/* Copyright (c)  1990,  L.P. Cygnarowicz, Cygan Systems, (408) 263-9180 */

/*  Development for SDSU Astronomy Lab by Greg Moore  2/10/95 */

/*  Development System SBus Generic Driver
	Definition file for users of the ASTRO devices */

/*--  Minor device Number encoding */
#define ASTRO_UNIT(dev)  minor(dev)

/*--  Procedure declarations */
int astro_open() ;
int astro_close() ;
int astro_read() ;
int astro_write() ;
int astro_ioctl() ;
int astro_vdcmd() ;


/* ------------ DMAIO CSR  Register bit assignments
31-28 		R		Device Id		1000
27-16 		R		Reserved		FFF
15		RW		ILAC.  Write this bit to 0.
14		R		TC
13		RW		Enable Byte Counter = 1
12-11		R		D Channel Pack Register Byte Address
10		R		D Channel DMA Cycle Request
9		RW		D Channel DMA Enable 1= Respond to D Chan requests
8		RW		D Channel Write Operation  1 = Write memory   0 = Read memory
7		RW		Reset   1 = Reset state
6		RW		Drain Buffer  1 = Write D Chan Pack reg to SBus memory and clear
				the Pack Count (Bits 3,2).  This bit clears automatically.
5		W		Flush Buffer. 1 = Reset Pack Count, Err Pending and TC bits.
4		RW		Interrupt Enable.  1 = Pass interrupt requests to SBus INTREQ
				Interrupt sources are D_IRQ*, Error Pending and TC reached.
3-2		R		D Channel Pack Count.  The number of valid bytes destined to
				be written to the SBus.
1		R		Error Pending.  Set if an error during a D Channel operation.
				Parity, protection or timeout.
0		R		Interrupt Pending (1 = Asserted.).  Latched OR of D_IRQ* or TC
-------*/

#define DMAIO_COUNT_ENABLE	0X00002000 /* 1 = enable Byte Counter, 0 = disable */
#define DMAIO_DMA_ENABLE	0X00000200 /* 1 = enable DMA operation  */
#define DMAIO_DMA_RW		0X00000100 /* 1 = Write memory   0 = Read memory */
#define DMAIO_DEV_RESET 	0X00000080 /* 1 = enable, 0 = disable */
#define DMAIO_DRAIN_BFR		0X00000040 /* 1 = Write back and clear, bit resets itself */
#define DMAIO_FLUSH_BFR		0X00000020 /* 1 = Reset Pack Count, Err Pending and TC bits */
#define DMAIO_INT_ENABLE	0X00000010 /* 1 = enable, 0 = disable */

#define DMAIO_TC         	0X00004000 /* 1 = TC Reached */
#define DMAIO_PACK_ADR     	0X00001800 /* 1 = marks the two bit address */
#define DMAIO_REQ_PEND		0X00000400 /* 1 = Active DMA request */
#define DMAIO_PACK_COUNT   	0X0000000c /* 1 = marks the two bit count */
#define DMAIO_ERR_PENDING	0X00000002 /* 1 = Active, clears on read */
#define DMAIO_INT_PENDING	0X00000001 /* 1 = Active, clears on read */
#define DMAIO_FASTER		0X00400000 /* 1 = Faster, 0 = Not as fast */