COMMENT * This file is used to generate DSP code for the second generation timing boards to operate a Boeing 256 x 256 BIB infrared array. * PAGE 132 ; Printronix page width - 132 columns ; Define a section name so it doesn't conflict with other application programs SECTION TIMBIB ; Include a header file that defines global parameters INCLUDE "timhdr.asm" APL_NUM EQU 0 ; Application number from 0 to 3 CC EQU COADDER+TIMREV4 SCR EQU $FFF0 ; SCI Control Register SSR EQU $FFF1 ; SCI Status Register SCCR EQU $FFF2 ; SCI Clock Control Register WRSCI EQU $FFF4 ; Write least significant byte to SCI port WRSCI0 EQU $FFF4 ; Write least significant byte to SCI port WRSCI1 EQU $FFF5 ; Write middle significant byte to SCI port WRSCI2 EQU $FFF6 ; Write most significant byte to SCI port SRAM_AD EQU $500 ; Address in timing board SRAM where coadder code is P_COADD EQU $E001 ; Start of coadder code in EEPROM RST_CA EQU 3 ; Timing board resets coadder board ; Specify execution and load addresses IF @SCP("DOWNLOAD","HOST") ORG P:APL_ADR,P:APL_ADR ; Download address ELSE ORG P:APL_ADR,P:APL_NUM*N_W_APL ; EEPROM address ENDIF ; Continuously reset array, checking for host commands every two columns CONT_RST MOVE #FRAME_INIT,R0 JSR =$200 WARN 'Application P: program is too large!' ; Make sure program ENDIF ; will not overflow ; **************** PROGRAM CODE IN SRAM PROGRAM SPACE ******************* ; Put all the following code in SRAM, starting at P:$200. IF @SCP("DOWNLOAD","HOST") ORG P:$200,P:$200 ; Download address ELSE ORG P:$200,P:APL_NUM*N_W_APL+APL_LEN ; ROM address ENDIF ; Delay for serial writes to the PALs and DACs by 8 microsec PAL_DLY DO #300,DLY ; Wait 8 usec for serial data transmission NOP DLY RTS ; Transmit a word to the coadder board over the SSI link XMT_CA JCLR #SSI_TDE,X:SSISR,* ; Continue if SSI XMT register is empty MOVEP X0,X:SSITX ; Write to SSI buffer RTS ; Wait for a 'DON' reply from the coadder board WT_DON JCLR #SSI_RDF,X:SSISR,* MOVEP X:SSIRX,A MOVE Y:24,X0 ; Check for argument less than 32 CMP X0,A JGE ERR_SM1 MOVE A,B MOVE #>7,X0 AND X0,B MOVE #>$18,X0 AND X0,A JNE $08,X0 CMP X0,A ; Test for 8 <= MUX number <= 15 JNE $10,X0 CMP X0,A ; Test for 16 <= MUX number <= 23 JNE 24,X0 ; Check for argument less than 32 CMP X0,A JGE ERR_SM2 REP #6 LSL A MOVE A,B MOVE #$1C0,X0 AND X0,B MOVE #>$600,X0 AND X0,A JNE $200,X0 CMP X0,A ; Test for 8 <= MUX number <= 15 JNE $400,X0 CMP X0,A ; Test for 16 <= MUX number <= 23 JNE Power reset BSET #HVEN,X:PBD MOVE #TST_RCV,X0 MOVE X0,X: Power reset BSET #HVEN,X:PBD MOVE #$002000,X0 ; Set lower half of clock driver MOVE X0,X:(R6) MOVE #$003000,X0 ; Set upper half of clock driver MOVE X0,X:(R6) ; Now ramp up the low voltages (+/- 6.5V, 16.5V) BCLR #LVEN,X:PBD ; LVEN = Low => Turn on +/- 6.5V, MOVE X:8,X0 CMP X0,A JLT 8 MOVE A1,Y: Wait States PCC EQU $FFE1 ; Port C Control Register PCDDR EQU $FFE3 ; Port C Data Direction Register PCD EQU $FFE5 ; Port C Data Register CRA EQU $FFEC ; SSI Control Register A CRB EQU $FFED ; SSI Control Register B SSISR EQU $FFEE ; SSI Status Register SSIRX EQU $FFEF ; SSI Receiver SSITX EQU $FFEF ; SSI Transmitter PBC EQU $FFE0 ; Port B Control Register PBDDR EQU $FFE2 ; Port B Data Direction Register PBD EQU $FFE4 ; Port B Data Register PCTL EQU $FFFD ; PLL control register IPR EQU $FFFF ; Interrupt Priority Register SCR EQU $FFF0 SSR EQU $FFF1 SCCR EQU $FFF2 STXL EQU $FFF4 SRXL EQU $FFF4 SSI_TDE EQU 6 ; SSI Transmitter data register empty SSI_RDF EQU 7 ; SSI Receiver data register full RCV_ERR EQU 2 ; Place in X: memory for SSI errors ; Board addresses RDFIFO EQU $C000 ; Read A/D FIFO into DSP WRCAFIFO EQU $C001 ; Write from DSP to coadder FIFO RSTFIFO EQU $C002 ; Reset both A/D and coadder FIFOs RSTSRAM EQU $8000 ; Start 32-bit mode pointer with D0-D23 (X: memory) ; Parallel port bit numbers, Port B SRAMADDR16 EQU 4 ; SRAM address line 16 SRAMADDR17 EQU 5 ; SRAM address line 17 SRAMADDR18 EQU 6 ; SRAM address line 18 SRAMADDR19 EQU 7 ; SRAM address line 19 GAIN EQU 8 ; A/D gain EF EQU 9 ; Bit number of incomimng FIFO empty flag HF EQU 10 ; Bit number of incoming FIFO half full flag ; More flags, Port C M24_32 EQU 2 ; 24- or 32-bit coaddition, Port C CAHF EQU 5 ; Cadder FIFO half full flag, on Port C ;************************************************************************** ; * ; Permanent address register assignments * ; R1 - Pointer to commands received pending processing * ; R2 - Pointer to processed commands * ; R3 - Pixel address of frame being coadded * ; R4 - Pixel address of frame being transmitted * ; R5 - RDFIFO address = $C000 * ; R6 - WRCAFIFO address = $C001 * ; * ;************************************************************************** ; Specify the load address for the coadder code IF @SCP("DOWNLOAD","HOST") ORG P:RST_ISR,P:$500 ; Download address ELSE ORG P:RST_ISR,P:RST_ISR+ROM_OFF ; ROM address ENDIF ; Special address for two words for downloading over coadder SCI port DC END_ADR ; Number of boot code words DC $0 ; Starting address of boot code ; After RESET jump to initialization code IF @SCP("DOWNLOAD","HOST") ORG P:RST_ISR,P:$500+2 ; Download address ELSE ORG P:RST_ISR,P:RST_ISR+ROM_OFF+2 ; ROM address ENDIF JMP 32,X1 ; Correct for the circular buffer ADD X1,A L_C32 CMP Y0,A ; Has it been incremented to RCV_BUF + NWORDS? JLT 1,X0 ; IBLKS = IBLKS - 1 SUB X0,A MOVE A,X:(COM_TBL+IBLKS-TABLE) ; Start coadding image data, checking to see if the CAFIFO needs replenishing MOVE #$00FFFF,X1 ; Set D23-D16 = 0 MOVEP #$1181,X:BCR ; Wait states for external memory accesses ; Ext. X:, Ext. Y, Ext. P:, Ext. I/O DO X:(R2)+,COADD ; Loop over number of coadds per frame DO #31,RD_LOOP ; Correct BIB value TST_PXL JSET #HF,X:PBD,TST_CA ; Wait for the FIFO to be half full MOVE X:(R5),A1 ; Read from the A/D FIFO DO #511,RD_PXLS ; Read 512 pixels = 1/2 of FIFO AND X1,A Y:(R3),B1 ; D23-D16 = 0; get coadded D23-D0 from SRAM ADD A,B X:(R5),A1 ; Co-add current pixel to on-going summation MOVE B1,Y:(R3)+ ; Write D23-D0 to SRAM RD_PXLS AND X1,A Y:(R3),B1 ; D23-D16 = 0; get coadded D23-D0 from SRAM ADD A,B ; Co-add current pixel to on-going summation MOVE B1,Y:(R3)+ ; Write D23-D0 to SRAM RD_LOOP ; Retrieve the last block at the end of the image separately DO #512,RD_END ; Correct BIB value JCLR #EF,X:PBD,* ; Wait for the FIFO to be not empty MOVE X:(R5),A1 ; Read from the A/D FIFO AND X1,A Y:(R3),B1 ; D23-D16 = zero; get coadded D23-D0 from SRAM ADD A,B ; Co-add current pixel to on-going summation MOVE B1,Y:(R3)+ ; Write D23-D0 to SRAM RD_END MOVE #$4000,X0 ; Reset the coadd buffer address MOVE R3,A ; to the beginning of the buffer SUB X0,A MOVE A1,R3 ; R3 is either $0 or $4000 COADD ; Swap the coadd and write buffer addresses BCHG #14,R3 ; Swap coadded image memory spaces BCHG #14,R4 MOVEP #$2281,X:BCR ; Wait states for ext. memory accesses JMP 1,X0 ; IBLKS = IBLKS - 1 SUB X0,A MOVE A,X:(COM_TBL+IBLKS-TABLE) JNE $6FF WARN 'Internal P: memory overflow!' ENDIF ENDSEC ; End of section COADD ; End of program END